[FastISel][AArch64] Add support for shift-immediate.

Currently the shift-immediate versions are not supported by tblgen and
hopefully this can be later removed, once the required support has been
added to tblgen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214345 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel][AArch64] Create helper functions to create the various multiplies on AArch64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214346 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel] Move the helper function isCommutativeIntrinsic into FastISel base class.

Move the helper function isCommutativeIntrinsic into the FastISel base class,
so it can be used by more than just one backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214347 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel][AArch64] Add {s|u}{add|sub|mul}.with.overflow intrinsic support.

This commit adds support for the {s|u}{add|sub|mul}.with.overflow intrinsics.
The unit tests for FastISel will be enabled in a later commit, once there is
also branch and select folding support.

This is related to <rdar://problem/17831117>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214348 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel][AArch64] Add branch folding support for the XALU intrinsics.

This improves the code generation for the XALU intrinsics when the
condition is feeding a branch instruction.

This is related to <rdar://problem/17831117>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214349 91177308-0d34-0410-b5e6-96231b3b80d8
[FastISel][AArch64] Add select folding support for the XALU intrinsics.

This improves the code generation for the XALU intrinsics when the
condition is feeding a select instruction.

This also updates and enables the XALU unit tests for FastISel.

This fixes <rdar://problem/17831117>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214350 91177308-0d34-0410-b5e6-96231b3b80d8
X86 asm parser: Use a loop to disambiguate suffixes instead of copy paste

This works towards making the Intel syntax asm matcher use a completely
different disambiguation strategy.

No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214352 91177308-0d34-0410-b5e6-96231b3b80d8
Refactor TLBIVAX and add tlbsx.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214354 91177308-0d34-0410-b5e6-96231b3b80d8