[Hexagon] Adding bit extraction and table indexing instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224610 91177308-0d34-0410-b5e6-96231b3b80d8
merge consecutive stores of extracted vector elements

Add a path to DAGCombiner::MergeConsecutiveStores() 
to combine multiple scalar stores when the store operands
are extracted vector elements. This is a partial fix for
PR21711 ( http://llvm.org/bugs/show_bug.cgi?id=21711 ).

For the new test case, codegen improves from:

   vmovss  %xmm0, (%rdi)
   vextractps      $1, %xmm0, 4(%rdi)
   vextractps      $2, %xmm0, 8(%rdi)
   vextractps      $3, %xmm0, 12(%rdi)
   vextractf128    $1, %ymm0, %xmm0
   vmovss  %xmm0, 16(%rdi)
   vextractps      $1, %xmm0, 20(%rdi)
   vextractps      $2, %xmm0, 24(%rdi)
   vextractps      $3, %xmm0, 28(%rdi)
   vzeroupper
   retq

To:

   vmovups	%ymm0, (%rdi)
   vzeroupper
   retq

Patch reviewed by Nadav Rotem.

Differential Revision: http://reviews.llvm.org/D6698



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224611 91177308-0d34-0410-b5e6-96231b3b80d8
[Hexagon] Removing old variants of instructions and updating references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224612 91177308-0d34-0410-b5e6-96231b3b80d8
CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224615 91177308-0d34-0410-b5e6-96231b3b80d8