Create Block Design
  - Add IP(s)
    * Add ZYNQ7 Processing System
    * Add XADC, GPIO, and Timer
  - Run Block Automation
  - Then, custom ZYNQ7 Processing System (because Vivado don't know how to connect periperal to Zynq7 ARM HW), again
    * Enable "GP Mater AXI Interface" (PS-PL Configuration)
    * Enable "I2C0 w MIO 10..11" (Periperal I/O Pins)
    * Enable "IRQ_F2P[15:0]" (Interrupts)
  - Run Conncion Automation
  - Click "Verify IP"
  - Right-click Block Design and Choose "Create HDL Wrapper"

Finally, Generate Bitstream