[r2dbe_vdif_lib] Added initial design to vdif block

This initial version of the library block has been tested and
compiled in the following model file on centos-nirvana:

~/Work/2014_06/09_r2dbe/r2dbe_10gbe_c.slx
~/Work/2014_06/09_r2dbe/r2dbe_10gbe_c/bit_files/
      r2dbe_10gbe_c_2014_Jun_27_1040.bof.gz

On vlbi-devel, I can test this bitcode by starting and ipython
session and connecting to roach2-05 up in the lab.  At the time
of writing this, it is 169.254.128.4

On vlbi-devel, I have developed a script to program and test
this bitcode:
~/2014_06/00_test_r2dbe/VDIF_test.py

This bof.gz is copied over to /srv/roach2_boot/current/boffiles/
on tenzing.

tenzing can also capture the data using a python script developed
by Rurik:
python /application/bin/udp-client.py 2

Which will capture 2 packets.

This test shows an important bug: namely that the first packet
of a stream of many packets is exactly 64 bits short (1 FPGA clock).

Simulation shows nothing like this.  A current explanation would
be that the eof flag ends up being set a clock earlier than shown
in simulation, which would create just the first packet to be short
and 1 clock of data to flow into the ten gbe buffer, waits for a while
then the next packet of data flows in.  No data seems to be
dropped, but pkts 2 through N seem to have the header misplaced by 2
32-bit data words (64 bits, 1 clock).