try to flatten out more chargen logic to meet timing.
try adding a wait state into JMP (indirect absolute) to see if that
helps fix the errors in that instruction.
work towards making fastram simulatable.
turn simulation specific memory map back off.
drop CPU speed to 48MHz while debugging CPU issues.
work work on making fastram simulable.
more work towards simulable fastram.  Still refuses to actually
write data to RAM. :/
got fastram working in simulation, provided it is single-ported.
so given CPU exclusive access for now.
update test rom to check that jmp indirect works in simulation.
it does.
try adding waitstate in a different place in JMP indirect to see
if that solves the bug we are seeing, which does not occur in
simulation.