i965: Add masks for more SURFACE_STATE fields

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965: Improve dumping of Gen7 SURFACE_STATE

Previously this was missing many interesting fields. Having them decoded
makes debugging views much easier.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965/Gen7: Only emit cube face enables for cubes.

This is not observed to actually fix anything, but the PRM says this
field must be zero for other surface types.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
i965: add struct and SFID for pixel interpolator messages

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Add #defines for new Broadwell math functions.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Add SFID #defines for media stuff.

While we probably won't ever use these, having them makes it easy to
share disassembler code between intel-gpu-tools and Mesa.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Add a new representation for Broadwell shader instructions.

Broadwell significantly changes the EU instruction encoding.  Many of
the fields got moved to different bit positions; some even got split
in two.

With so many changes, it was infeasible to continue using struct
brw_instruction.  We needed a new representation.

This new approach is a bit different: rather than a struct, I created a
class that has four DWords, and helper functions that read/write various
bits.  This has several advantages:

1. We can create several different names for the same bits.  For
   example, conditional modifiers, SFID for SEND instructions, and the
   MATH instruction's function opcode are all stored in bits 27:24.

   In each situation, we can use the appropriate setter function:
   set_sfid(), set_math_function(), or set_cond_modifier().  This
   is much easier to follow.

2. Since the fields are expressed using the original 128-bit numbers,
   the code to create the getter/setter functions follows the table in
   the documentation very closely.

To aid in debugging, I've enabled -fkeep-inline-functions when building
gen8_instruction.c.  Otherwise, these functions cannot be called by
gdb, making it insanely difficult to print out anything.

Kenneth Graunke wrote most of this code.  Damien Lespiau ported it to
C99.  Xiang Haihao added media fields.  Zhao Yakui added indirect
addressing support.  Eric Anholt added an assertion to make sure that
values fit in the alloted number of bits.

v2: Update for brw_reg_type_to_hw_type(), which necessitates passing
    brw_context pointers around everywhere.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Acked-by: Matt Turner <mattst88@gmail.com>
i965: Implement a disassembler for Broadwell's new instruction encoding.

Heavily based on Keith Packard's existing brw_disasm.c code.  I've tried
to go through most of the pieces (like SFIDs) and update the lists to
include features added in recent generations.

v2: Port to use the C-based instruction emitters.  This allows us to use
    C99 array initializers, which tidies up some of the code.

v3: Improve decoding of render target write messages.

v4: Update for BRW_REGISTER_TYPE becoming an abstraction.

v5: Rebase on Chris Forbes' SFID message defines.

v6: Fix disassembly of UV immediates; remove silly casts.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: Add a new infrastructure for generating Broadwell shader assembly.

This replaces the brw_eu_emit.c layer for Broadwell.  It will be
used by both the vector and scalar shader backends.

v2: Port to use the C-based instruction representation.

v3: Fix destination register type for CMP.

v4: Pass brw to gen8_instruction functions (required by rebase).

v5: Remove bogus assertion on math instructions (caught by Piglit).

v6: Remove more restrictions on math instructions (caught by Eric).
    Make ADDC and SUBB helpers set accumulator writes, like MAC and
    MACH (caught by Matt).

v7: Don't implicitly force ALU3 operations to SIMD8 (we've been able
    to do SIMD16 versions since Haswell, but didn't when I originally
    wrote this code).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Create a new vec4 backend for Broadwell.

This replaces the old vec4_generator backend.

v2: Port to use the C-based instruction representation.  Also, remove
    Geometry Shader offset hacks - the visitor will handle those instead
    of this code.

v3: Texturing fixes (including adding textureGather support).

v4: Pass brw_context to gen8_instruction functions as required.

v5: Add SHADER_OPCODE_TXF_MCS support; port DUAL_INSTANCED gs fixes
    (caught by Eric).  Simplify ADDC/SUBB handling; add comments to
    gen8_set_dp_message calls (suggested by Matt).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Create a new fragment shader backend for Broadwell.

This replaces the old fs_generator backend.

v2: Port to the C-based representation of assembly instructions.
    Fix texturing after the texture-grf merge.

v3: Add high quality derivative support.  Fix SET_SIMD4X2_OFFSET.

v4: Pass brw_context to gen8_instruction functions as required.

v5: Fixes for MRT, as well as zero render targets (alpha test only).

v6: Replace n-wide with SIMDn in comments and messages; port over
    Topi's blorp-generator changes; add missing TXF_MCS opcode,
    fix missing high quality derivatives for DDX; fix typo (all caught
    by Eric).  Simplify ADDC/SUBB handling; drop "Used only on Gen6+"
    comment (caught by Matt).  Emit SIMD16 versions of three source
    instructions (caught by both Eric and Matt).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Use the Sandybridge VUE format on Broadwell as well.

It hasn't changed.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
i965: Update invariant state for Broadwell.

The only difference is that STATE_SIP takes a 48-bit address, so we need
to output two zeroes.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: Double the push constant space multipliers on Broadwell too.

Broadwell has 2Kb push constant size increments like Haswell GT3.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>