Simplify and fix incorrect comment. No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208272 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: support FK_SecRel_2 relocations on WoA

This adds FK_SecRel_2 relocation support to ARM.  This enables the building of
object files for armv7-windows-msvc which enables CodeView line tables for
debugging as opposed to armv7-windows-itanium which currently uses DWARF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208273 91177308-0d34-0410-b5e6-96231b3b80d8
test: fix silly typo

Oh silly Darwin and your case insensitive file system.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208274 91177308-0d34-0410-b5e6-96231b3b80d8
[modules] Add missing #include.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208276 91177308-0d34-0410-b5e6-96231b3b80d8
SCEV: Use I = vector<>.erase(I) to iterate and delete at the same time

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208282 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64/ARM64: Port NEON post-increment load/store with 2/3/4 vectors to ARM64 backend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208284 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "SCEV: Use I = vector<>.erase(I) to iterate and delete at the same time"

as committed in r208282. The original commit was incorrect.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208286 91177308-0d34-0410-b5e6-96231b3b80d8
Move late partial-unrolling thresholds into the processor definitions

The old method used by X86TTI to determine partial-unrolling thresholds was
messy (because it worked by testing target features), and also would not
correctly identify the target CPU if certain target features were disabled.
After some discussions on IRC with Chandler et al., it was decided that the
processor scheduling models were the right containers for this information
(because it is often tied to special uop dispatch-buffer sizes).

This does represent a small functionality change:
 - For generic x86-64 (which uses the SB model and, thus, will get some
   unrolling).
 - For AMD cores (because they still currently use the SB scheduling model)
 - For Haswell (based on benchmarking by Louis Gerbarg, it was decided to bump
   the default threshold to 50; we're working on a test case for this).
Otherwise, nothing has changed for any other targets. The logic, however, has
been moved into BasicTTI, so other targets may now also opt-in to this
functionality simply by setting LoopMicroOpBufferSize in their processor
model definitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208289 91177308-0d34-0410-b5e6-96231b3b80d8
Use a vector of unique_ptrs to fix a memory leak introduced in r208179.

Also removed an inaccurate comment that stated that a DenseMap was used as
storage for the ListInit*'s. It's currently using a FoldingSet.

I expect there's a better way to fix this but I haven't found it yet. FoldingSet
is incompatible with the Pool template and I'm not sure if FoldingSet can be
safely replaced with a DenseMap of computed FoldingSetID's to ListInit*'s.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208293 91177308-0d34-0410-b5e6-96231b3b80d8
[asan] Preserve flags in asm instrumentation.

Patch by Yuri Gorshenin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208296 91177308-0d34-0410-b5e6-96231b3b80d8
ARM64: make sure FastISel emits SSA MachineInstrs

We need to use a temporary register for a 2-step operation like REM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208297 91177308-0d34-0410-b5e6-96231b3b80d8
Test commit. Added blank line.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208298 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Implement tlbp, tlbr, tlbwi, and tlbwr

Reviewers: vmedic, dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3571

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208301 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Marked up instructions added in MIPS-II and tested that IAS for -mcpu=mips1 does not accept them

Summary:
A small number of instructions are rejected with the wrong error message.
These have been placed in a separate test for now. There seems to be some
parsing quirk that triggers when these instructions are disabled.

Depends on D3571

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3647

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208305 91177308-0d34-0410-b5e6-96231b3b80d8
[ARM64-BE] Teach fast-isel about how to set up sub-word stack arguments for big endian calls.

SelectionDAG already knows about this, but fast-isel was ignorant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208307 91177308-0d34-0410-b5e6-96231b3b80d8
Revert test commit. Removed blank line.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208308 91177308-0d34-0410-b5e6-96231b3b80d8
Add isOSFreeBSD triple test

For http://reviews.llvm.org/D3448


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208309 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Implement l[wd]c3, and s[wd]c3.

Summary:
These instructions were added in MIPS-I, and MIPS-II but were removed in
MIPS-III. Interestingly, GAS continues to accept them when assembling for
MIPS-III.

For the moment, these instructions will follow GAS and accept them for
MIPS-III and newer but this will be tightened up when the invalid-*.s
tests are added.

Depends on D3647

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3648

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208311 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a spelling error

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208314 91177308-0d34-0410-b5e6-96231b3b80d8
ARM big endian function argument passing

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208316 91177308-0d34-0410-b5e6-96231b3b80d8