flush mul ops
ctrl: code cleanup, no functional change
add dtlb_priv to lsu_exc
registerfile: code cleanup, no functional change
writeback: make sure exception pc gets written on do_exception
quit on unsupported tb* instructions
implement tbs and tbri instructions
connect ex_op_store to dtlb_write fault signal
remove 'assert' on tbri/tbs instructions
avoid writing tlb entries on flush
lsu: abort writes on flush
ctrl: remove a couple of debug prints
top: format cleanup + remove empty parameter lists
remove empty parameter lists

+ minor whitespace cleanups
decode: remove redundant wire

id_bubble is already declared as an output port
fix wire vs reg vs wire

this is one of the things verilog just got wrong...