Convert tools/regression/lib/libc/stdio/test-fpclassify into an ATF testcase and
Rename as lib/libc/stdio/fpclassify2_test

Sponsored by: EMC / Isilon Storage Division
Indent a couple lines properly and expand a comment.  No functional changes.
Skip the long-double epsilon checks on FreeBSD/i386

Sponsored by: EMC / Isilon Storage Division
Reset errno to 0 before running scalbn to be sure that the tested errno is
valid

Sponsored by: EMC / Isilon Storage Division
Alias isinff to isinf on FreeBSD

isinf on FreeBSD automatically picks the appropriate type per math.h

Sponsored by: EMC / Isilon Storage Division
- Expect exp2_powers to fail on FreeBSD/i386
- Expect exp2_values to fail on FreeBSD due to the small epsilon

Sponsored by: EMC / Isilon Storage Division
- Skip over the testcases that call cbrtl on platforms where LDBL_PREC == 53
(arm, mips, powerpc). This fixes the build on these platforms, based on some
ad hoc tinderbox runs I did a while ago
- Skip cast the arguments to powl as long double so powl properly interprets
those arugments at compile-time when picking the type

Sponsored by: EMC / Isilon Storage Division
Do not do a cache invalidate on a PREREAD sync that is also a PREWRITE sync.
The PREWRITE handling does a writeback of any dirty cachelines, so there's
no danger of an eviction during the DMA corrupting the buffer.  There will
be an invalidate done during POSTREAD, so doing it before the read too is
wasted time.
Do the cache invalidate sequence from the outermost to innermost, required
for correct operation.

Submitted by:	Michal Meloun <meloun@miracle.cz>
Correct the sequence of busdma sync ops involved with PRE/POSTREAD syncs.

We used to invalidate the cache for PREREAD alone, or writeback+invalidate
for PREREAD with PREWRITE, then treat POSTREAD as a no-op.  Prefetching on
modern systems can lead to parts of a DMA buffer getting pulled into the
caches while DMA is in progress (due to access of "nearby" data), so it's
mandatory to invalidate during the POSTREAD sync even if a PREREAD
invalidate also happened.

In the PREREAD case the invalidate is done to ensure that there are no
dirty cache lines that might get automatically evicted during the DMA,
corrupting the buffer.  In a PREREAD+PREWRITE case the writeback which is
required for PREWRITE handling is suffficient to avoid corruption caused
by eviction and no invalidate need be done until POSTREAD time.

Submitted by:	Michal Meloun <meloun@miracle.cz>
No functional changes.  Remove a couple outdated or inane comments and
add new comment blocks describing why the cache maintenance sequences are
done in the order they are for each case.