ARM: 7122/1: localtimer: add header linux/errno.h explicitly

Per the text in  Documentation/SubmitChecklist as below, we should
explicitly have header linux/errno.h in localtimer.h for ENXIO
reference.

1: If you use a facility then #include the file that defines/declares
   that facility.  Don't depend on other header files pulling in ones
   that you use.

Otherwise, we may run into some compiling error like the following one,
if any file includes localtimer.h without CONFIG_LOCAL_TIMERS defined.

  arch/arm/include/asm/localtimer.h: In function ‘local_timer_setup’:
  arch/arm/include/asm/localtimer.h:53:10: error: ‘ENXIO’ undeclared (first use in this function)

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: mm: use TTBR1 instead of reserved context ID

On ARMv7 CPUs that cache first level page table entries (like the
Cortex-A15), using a reserved ASID while changing the TTBR or flushing
the TLB is unsafe.

This is because the CPU may cache the first level entry as the result of
a speculative memory access while the reserved ASID is assigned. After
the process owning the page tables dies, the memory will be reallocated
and may be written with junk values which can be interpreted as global,
valid PTEs by the processor. This will result in the TLB being populated
with bogus global entries.

This patch avoids the use of a reserved context ID in the v7 switch_mm
and ASID rollover code by temporarily using the swapper_pg_dir pointed
at by TTBR1, which contains only global entries that are not tagged
with ASIDs.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
ARM: mm: allow ASID 0 to be allocated to tasks

Now that ASID 0 is no longer used as a reserved value, allow it to be
allocated to tasks.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
ARM: mm: Optimise the v7 Dcache flush all routine.

The current algorithm flushes using the SET and WAY, where it iterates over
a given SET in all the WAYS and to the next SET. Change this so that every
successive flush address will go to in to the alternate EMIF(1/2), there by
utilising the full bandwidth. Also iterating all the SETS of a given WAY,
and then switching to the next way can reduce the possibility of frequent
change in the row bits during successive transactions of the DDR memory.
This will help in reducing the ROW open/close time.

Signed-off-by: Marquette Anderson <m-anderson13@ti.com>
ARM: mm: Add v7_flush_dcache_by_level() API.

On ARMv7 based SOC with an integrated L2 cache, there is a need to have a flush
api to operate on each cache level. In few low power modes, L2 cache is retained
where as L1 is lost. The current v7_flush_dcache_all(), flushes all the levels
and it would be quite expensive.

So introduce v7_flush_dcache_by_level() API which takes a parameter (cache
level), and flush only on that level.

The set/way loops can be shared between v7_flush_dcache_by_level() and
v7_flush_dcache_all(). I didn't do that in this version to avoid indirections
and primiarily not to touch the existing and widely used API.

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
ARM: OMAP: hwmod: Fix unwanted warns at boot

Complain only if clkdm association is missing from
both clock node as well as hwmod node. On OMAP4+, the
clkdm association is moved to hwmod from the clock.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
ASoC: Trivial formatting fix in soc-core.c

Utterly trivial but it annoys me.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@ti.com>