began adding loop+delay and coinductive stream eval. Split CoreC into combinational and seq parts
stream-based simulation function defined, handling delay+loop constructor
stream eval tested with sample and working OK, using Stream from stdlib
made CoreC be the possibly sequential type, CombC is purely combinational
made sequential CoreC have strcutural constructors also, evaluating them
separated ripple-carry sample into own file, was taking too long to load
close to having generic-sized mux, missing instances
written high-level datatype for sequential circuits
hold back general muxes ATM, modeled 1-bit reg
high-level simulation function for sequential circuits
FIXED error on argument order of register, had to swap
using Circuit module parameterized
having troubles proving simple coinductive facts abour register
left hole with bisimilarity proof which I am stuck at