bank: add re to CSRStorage

being able to know when a register is updated is useful in many cases and avoid having to handle another register for that.
re is asserted when the the last CSR of the Compound is written. Software must also write Compound in the right order.
remove trailing whitespaces
_Endpoint: allow direct access of payload elements
use new direct access on endpoints
DMAWriteController: fix Demultiplexer layout
flow/actor/Endpoint: clean up __getattr__
Raise exception when not using correct boolean operators
fhdl/verilog: fix tristate to instance connection
xilinx_vivado: add hierarchical utilization report
xilinx_vivado: use .bat on Windows platforms (otherwise Vivado uses Unix scripts...)
kc705: add Ethernet pins
crc: generate error asynchronously to avoid stalling the flow and simplify
bus/csr: add configurable address_width (needed more than 32 modules with CSR)
flow/actor, actorlib/structuring: add packet support
Merge branch 'master' of github.com:m-labs/migen
actorlib/structuring: add Converter

Converter enables easy conversions of data width on dataflows.
It handles the 3 possibles cases:
- downconverter
- upconverter
- direct connection when data width are identical.
actorlib/structuring: add Pipeline

Pipeline enables easy cascading of dataflow modules.
DataFlowGraph can eventually use it to implement the
add_pipeline method to avoid duplicating things.
actorlib/structuring/Pipeline: make 'busy' a signal
test/test_size: fix slice comparison
vpi/ipc: fix decoding of index buffer