hdl/modules/*/wb_fmc130m_4ch.vhd: comment out unused signals

Thse were causing lgic contention with some specific Xilinx
XST options, particularly KEEP_HIERARCHY = SOFT, to keep
the hierarchy so we could properly apply some AREA constraints.
The tool would GND these NETS anyway.
hdl/modules/*/fmc_adc_buf.vhd: change LVDS to LVCMOS

For single-ended pins, we can't use LVDS standard,
so we default to LVCMOS25. If the standard is actually
different from this, we could still override it in the UCF
file
hdl/modules/*/fmc_adc_data.vhd: add attributes to keep pipeline

If we let the synthesis tool in its defauts attributes, the
pipeline gets removed and moved into a SRL primitive, causing
PCBs having ADC FMC data lines routed to oppositte FPGA I/O
banks to not meet timing. With these attributes we intruct
XST and MAP to keep the pipeline and not suck them into an
SRL, which would hurt the ability by MAP and PAR to move
the pipeline registers around to meet timing.
hdl/top/afc_v1/*/sys_pll.vhd: add g_divclk_divide attribute
hdl/top/afc_v1/*/dbe_bpm_dsp.vhd: change PLL attributes
hdl/top/ml_605/*/position_calc_core.ucf: update DSP constraints

This was not supposed to be here, but we include it here,
as to not loose the changes
hdl/syn/afc_v1/*/Manifest.py: add ise_tool parameter

In the new version of hdlmake, we need to supply
the ISE version we want to use
hdl/ip_cores/dsp-cores: update submodule reference
hdl/ip_cores/general-cores: update submodule reference