More Zynq progress for bitstream building
components/delay.rcc/delay.c: warning
hdl/platforms/zed/Makefile: update core PS7 primitive version to 4.03a
hdl/platforms/zed/ps.ucf: remove
hdl/platforms/zed/zed.mk: don't specialize anything yet.
hdl/platforms/zed/zed.vhd: don't deal with PS signals at all at top level
hdl/platforms/zed/zed.xml: ditto
hdl/platforms/zed/zed_ps.vhd: ditto, plus sync with XPS output
hdl/platforms/zed/zynq_pkg.vhd: ditto
hdl/primitives/platform/timeService.v: fix some warnings
tools/cdk/include/hdl/hdl-assembly.mk: make container xst use exact part
tools/cdk/include/hdl/hdl-assy.mk: remove
tools/cdk/include/hdl/hdl-config.mk: remove
tools/cdk/include/hdl/hdl-platform.mk: force platform worker to use exact part
hdl/platforms/zed/zed.ucf: the UCF for our true external signals
Zynq is now full function without data plane, more doc/cookbook/cleanup to come, then DP
core/container/hdl/include/BusDriver.h: enable loading the bitstream when there is none loaded
core/container/hdl/include/HdlDriver.h: ditto
core/container/hdl/src/ocpihdl_main.cxx: ditto
core/container/hdl/src/BusDriver.cxx: ditto and implement bitstream loading from .bit.gz files:
-- Implemented without scripts and without temporary files
-- Does decompression on the fly with zlib
-- Does .BIT --> .BIN conversion on the fly in software
-- Thus the basic bitstream files (.bit.gz) are the same for every Xilinx platform
core/container/hdl/src/HdlDevice.cxx: catch bus errors on probing:
-- Allow us to probe for a bitstream when there is no bitstream loaded and not crash
core/container/hdl/src/HdlDriver.cxx: add "bus" control driver for zynq
-- and generically allow drivers to know whether they are only being opened for "load".
core/container/hdl/src/HdlWciControl.cxx: don't assume stop is implemented everywhere
core/local/util/misc/include/OcpiUtilMisc.h: add OU::swap32
hdl/platforms/alst4/Makefile: update to use hdl-platform.mk
hdl/platforms/alst4x/Makefile: ditto
hdl/platforms/isim_pf/Makefile: ditto
hdl/platforms/ml605/Makefile: ditto
hdl/platforms/modelsim_pf/Makefile: ditto
hdl/platforms/ml605/ml605.ucf: comment out unused constraints so we can strictly check them
hdl/platforms/zed/axi2cp.vhd: rewrite to deal properly with 2 word read/write bursts:
-- this was to support the ARM core doing 64 bit loads and stores.
-- not full burst support - just 8/16/32/64 bit loads and stores
hdl/platforms/zed/zed.vhd: some more debug LEDs for now
hdl/platforms/zed/zynq_pkg.vhd: comments
jkvm6.sh: use new cleaner scheme for these env setting scripts
tools/cdk/include/hdl/xst.mk: cleaner and correctly ordered library lists
tools/cdk/scripts/ocpisetup.sh: make usable for run-time-only systems
tools/cdk/scripts/showRuntimeHost: enable recognition of zed/zynq
tools/ocpigen/src/parse.cxx: assume "stop" support for VHDL, but not verilog
tools/ocpigen/src/wip_HDL.cxx: ditto
tools/ocpigen/src/wip_OCL.cxx: warning
extra files added for zynq
updated README for initial Zynq checkout