msm: clock-generic: Add get_rate op for ext clocks

The ext clock type may sometimes need to report the
rate of its parent. Add the get_rate op to allow this.

Change-Id: Id22e6a52aa36422fe4583d9c062a962f3399b6c4
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
msm: clock-8610: Switch camera muxes to generic mux implementation

The camera mux implementation used ops in clock-local2
written specifically for the 8610 camera mux clocks.
Switch to the more generic mux implementation in the
clock-generic library, and delete the 8610 specific
implementation.

Change-Id: I52da122ab46f6de51ad23fbd64398e5a3347d350
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
msm: clock-generic: Allow separate enable/mux-select registers

Some muxes may have independent registers to control
mux selection and enable/disable. Add an additional
field to the mux clock struct to support this.

Change-Id: I436ca0ba48d186fb76d4e5585be4dd1f41fe7739
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
msm: clock-generic: Move mux_reg_ops to clock-local2

To keep clock-generic generic, move the mux_reg_ops to
clock-local2, since clock-generic is really not meant
to touch hardware directly.

Conflicts:

        arch/arm/mach-msm/clock-local2.h

Change-Id: Ic2ffd2383c1a8a82efaa5e6c5b2185039a30259a
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
msm: clock-generic: Add a get_rate op for slave dividers

Clk_get_rate on slave dividers currently returns the cached
rate. However, in case of some fixed dividers, the parent
rate may change without set_rate ever being called on the
slave divider clock. Therefore, add a get_rate op that
divides the parent clock rate and returns the result.

Change-Id: I94dbd7238b3cd4538f8ffaea6a1a146b4432704c
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
msm: clock-generic: Add a combined mux_div clock

This new clock type is intended to handle certain special cases which
cannot be implemented with the existing mux and divider clock types.

Hardware may support switching both the parent clock and the divider
at the same time. This avoids generating intermediate frequencies from
either the old parent clock and new divider or new parent clock and old
divider combinations.

Extend the "safe parent" concept of the mux clock to a "safe freq".
"safe freq" is guaranteed to be within the fmax requirements for the
lowest voltage level, so it is safe to switch to at any time. It must be
defined when one of the parent clocks must be disabled in order to switch
rates.

Change-Id: I0163be99f2d14b38ce2c2d885df4d68e5c564dde
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
msm: clock-mdss-8974: Set min/max div for fixed divider clocks

Fixed dividers in mdss might not be handed off successfully during
init. Add in min/max_div field to make sure clk_round_rate will
still work correctly even if handoff fails.

Conflicts:

	arch/arm/mach-msm/clock-mdss-8974.c

Change-Id: I9f539a35c44455e748bc47ccef4b482f535d9ebf
Signed-off-by: Junjie Wu <junjiew@codeaurora.org>
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
msm: pm-8x60: Use generic clk apis during power collapse

The power management code calls in acpuclk code directly to switch to a
always on clock source during power collapse there by turning off the
HFPLL during any power collapse. The Krait clock management is switching
to use clocks ops model. To necessitate the change, the power management
code will register for CPU/L2 clock sources and disables the
corresponding clocks during power collapse.

Add a DT node to indicate if the clock sources are synchronized across
the cores/L2, to prevent querying on clock sources that might not be
available on certain targets. Also, clk_get() doesn't currently support
deferred probe, change the compile order to include pm-8x60 after clocks
driver to ensure that clock drivers get probed before pm-8x60.

Change-Id: I671296064dda93f1d2226e6ae059d827c4c00890
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
ARM: dts: msm: Add clock-krait and msm-cpufreq device for msm8974

The clock-krait device is a more accurate and detailed representation of
the Krait subsystem clock tree than the acpuclk device. Registering and
probing this device allows the use of standard clock APIs to control CPU/L2
clocks. So, replace the acpuclk device with a clock-krait device.

When exposing the CPU/L2 clock tree through clock APIs, the cpufreq driver
has to handle the L2 and memory BW voting. So, add the msm-cpufreq device
to provide the required data and to avoid breaking cpufreq functionality.

To make sure the switchover doesn't break power management code, also set
the PM device flag that indicates cpu clocks are controlled through
standard clock APIs.

Also update clock 8974 lookup table for clock-krait device.

Conflicts:

	arch/arm/boot/dts/msm8974pro-ac.dtsi
	arch/arm/boot/dts/msm8974pro.dtsi

Change-Id: I8b563199ffcca717603e98a9878314ff34fba7f7
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
clock-mdss-8974: Switch HDMI clocks to use the new PLL implementation

This change cleans up the HDMI VCO/PLL implementation. It implements
the HDMI VCO clock and uses generic div and mux clocks to align to
the HDMI PLL architecture.

CRs-Fixed: 456315
Change-Id: I19ef344aafc954935cd6d236f3725bf168658ec9
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
msm: clock-mdss-8974: Enable AHB clock before register access

Enable the MDSS AHB clock for proper HDMI PHY PLL register
access. Disable the MDSS AHB clock after register access.

Change-Id: Ice8e723333f3c041bc1cffa2ebc8d7d40a8817d2
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
msm: clock-mdss-8974: Proper hdmi set rate

Do not call set rate if the rate is zero. Reset the flag which sets
the rate on cable disconnect so that next cable connect can set the
rate again.

Change-Id: Ieb8eed3760c4b285182ae47d732352771d13b020
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
msm: clock-mdss-8974: Dynamic HDMI PHY-PLL configuration

Implement the  HDMI PHY PLL calculator to dynamically configure the
HDMI PLL VCO to any supported pixel rate within the supported range.

Change-Id: I5665509aeaf54132ae711e3c4c9be542b25b8241
Signed-off-by: Ajay Singh Parmar <aparmar@codeaurora.org>
msm: acpuclock-cortex: Fix off by one error for large frequency tables

If a frequency table was greater than a certain size, data will be written
past the end of an array. Fix the loop conditions to prevent this.

CRs-fixed: 561651
Change-Id: If7bafcf79c044877f4a29c2437c139d23aa1fb32
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>
msm: clock-mdss: correct check for MDSS GDSC status

MDSS GDSC may be always on but clock is off in reset state.
Therefore, the correct way to check GDSC status is read both
gdsc enable bit and the clock reset bit. This change is
necessary to prevent potential crashes that may occur if
MDSS registers are accessed when MDSS GDSC is not enabled.

Change-Id: I501450beed3ea798329b34b96f2966cfefc901c2
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
Signed-off-by: Pawan Kumar <pavaku@codeaurora.org>
msm: clock-mdss: Update PLL enable sequence for MSM8226

Update the PLL enable sequence to address PLL lock failures
seen sporadically on MSM8226.

Change-Id: I44c42f92d92d20ca8dece1ed516a9fa8db5eda44
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
msm: clock-mdss: Do not toggle lock detect during handoff

If continuous splash screen feature is enabled, then the DSI
clocks are left on in the bootloader. When the kernel boots
up, te DSI PLL lock status is checked in order to determine
whether these clocks should be handed off or not. Ensure that
the lock detect register is not toggled at this time to avoid
any blinks in the display.

Change-Id: Ica8c42e260d9b3ceffda885b1942fab945f60c86
CRs-Fixed: 506037
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
msm: Update dynamic HDMI clock API usage

Change-Id: Iaf73517bd41a8656a72be2e1d8768c1cd17b6082
msm: cpubw-krait: Vote for Krait-DDR bandwidth by monitoring transactions.

The Krait L2 performance monitor counters have the capability to count the
no. of read/write transactions going out the master ports. They also have
the capability to raise interrupts when they overflow. This driver uses
those counters to determine the true usage of DDR from the Krait processor
subsystem and then uses that measured bandwidth to vote for Krait-DDR BW
requirements.

The driver provides various other tunables that allow it to be tuned more
in favor of power or performance.

- io_percent: The percentage of the CPU time that can be spent waiting on
  memory I/O. Lower value is better performance and worse power.

- sample_ms: The sampling period in milliseconds. This only affects the
  sampling period when DDR use is ramping down or is increasing very slowly
  (See tolerance_percent).

- tolerance_percent: The minimum increase in DDR use, compared to previous
  sample, that will trigger an IRQ to immediately bump up the bandwidth
  vote. It's expressed as a percentage of the previous sampled DDR use.

- decay_rate: The parameter controls the rate at which the history is
  forgotten when ramping down. This is expressed as a percentage of history
  to be forgotten.  So 100% means ignore history, 0% mean never forget the
  historical max. The default 90% means forget 90% of history each time.

- guard_band_mbps: This is a margin that's added to the measured BW (and
  hence also the Bus BW votes) that's present to account for the time it
  takes to ramp up the DDR BW while the CPU continues to use the DDR.

- bw_step: All BW votes are rounded up to multiples of bw_step. The default
  value is 200 MB/s that turns out to 25 MHz. A smaller value would mean
  more frequent bus BW changes. A higher value would mean less frequent BW
  vote updates, but also means at times an unnecessarily higher BW vote
  (due to the rounding up).

- enable: A boolean flag to control if the driver is enabled or disabled.
  Disabling the driver leave the bandwidth vote at the last voted value.

Change-Id: I021ae64c71451e272a13be2841bfda4d121d318d
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Signed-off-by: Amir Vajid <avajid@codeaurora.org>
Signed-off-by: Chester Kener <Cl3Kener@gmail.com>

Conflicts:
	arch/arm/mach-msm/Makefile