net: can: c_can: Add syscon/regmap RAMINIT mechanism

Some TI SoCs like DRA7 have a RAMINIT register specification
different from the other AMxx SoCs and as expected by the
existing driver.

To add more insanity, this register is shared with other
IPs like DSS, PCIe and PWM.

Provides a more generic mechanism to specify the RAMINIT
register location and START/DONE bit position and use the
syscon/regmap framework to access the register.

Signed-off-by: Roger Quadros <rogerq@ti.com>
net: can: c_can: Add support for START pulse in RAMINIT sequence

Some SoCs e.g. (TI DRA7xx) need a START pulse to start the
RAMINIT sequence i.e. START bit must be set and cleared before
checking for the DONE bit status.

Signed-off-by: Roger Quadros <rogerq@ti.com>
net: can: c_can: Disable pins when CAN interface is down

DRA7 CAN IP suffers from a problem which causes it to be prevented
from fully turning OFF (i.e. stuck in transition) if the module was
disabled while there was traffic on the CAN_RX line.

To work around this issue we select the SLEEP pin state by default
on probe and use the DEFAULT pin state on CAN up and back to the
SLEEP pin state on CAN down.

Signed-off-by: Roger Quadros <rogerq@ti.com>
net: can: c_can: Add support for TI DRA7 DCAN

DRA7 SoC has 2 CAN IPs. Provide compatible IDs and RAMINIT
register data for both.

Signed-off-by: Roger Quadros <rogerq@ti.com>
net: can: c_can: Add support for TI am3352 DCAN

AM3352 SoC has 2 DCAN modules. Add compatible id and
raminit driver data for am3352 DCAN.

Signed-off-by: Roger Quadros <rogerq@ti.com>
ARM: dts: dra7: Add syscon regmap for CORE CONTROL area

Display and DCAN drivers use syscon regmap to access some registers
in the CORE control area. Add the syscon regmap node for this
area.

Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
ARM: dts: DRA7: Add DCAN nodes

The SoC supports 2 DCAN nodes. Add them.

Signed-off-by: Roger Quadros <rogerq@ti.com>
ARM: dts: dra7-evm: Add CAN support

The board has 2 CAN ports but only the first one can be used.
Enable the first CAN port.

WAKEUP0 pin doesn't have INPUT enable bit so we just disable
weak PULLs.

The second CAN port cannot be used without hardware modification
so we don't enable the second port.

Signed-off-by: Roger Quadros <rogerq@ti.com>
ARM: dts: dra72-evm: Add CAN support

The board has 2 CAN ports but only the first one can be used.
Enable the first CAN port.

WAKEUP0 pin doesn't have INPUT enable bit so we just disable
weak PULLs.

The second CAN port cannot be used without hardware modification
so we don't enable the second port.

Signed-off-by: Roger Quadros <rogerq@ti.com>
ARM: dts: am4372: Add control module syscon node

Use syscon regmap to expose the Control module register space.
This register space is shared between many users e.g. DCAN, USB, display, etc.

Signed-off-by: Roger Quadros <rogerq@ti.com>
ARM: dts: am4372: Add DCAN nodes

The SoC contains 2 DCAN modules. Add them.

Signed-off-by: Roger Quadros <rogerq@ti.com>
arm: dts: am437x-gp: Add dcan support

Add DCAN support for AM437x GP EVM with both DCAN instances.

[Roger Q] Updated output pin to not use pull up.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: George Cherian <george.cherian@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
ARM: dts: am33xx: Add control module syscon node

Use syscon regmap to expose the Control module register space.
This register space is shared between many users e.g. DCAN, USB, display, etc.

Signed-off-by: Roger Quadros <rogerq@ti.com>
ARM: dts: am33xx: Update DCAN nodes

Add "raminit-syscon" property to specify the RAMINIT register.
Add clock information.
Rename can nodes from "d_can" to "can" to be compliant
with the ePAPR specs.

Signed-off-by: Roger Quadros <rogerq@ti.com>
ARM: dts: am335x-evm: Add DCAN1 details

DCAN1 is routed to CAN port (J11) when Profile 1 is selected on the
profile selection switch.
Provide information for DCAN1 pins and node but keep it disabled
by default. User has to manually enable it if Profile 1 is chosen.

Signed-off-by: Roger Quadros <rogerq@ti.com>
HACK: ARM: DRA7: clockdomain: Fix DCAN1 RAMINT

Disable HW_AUTO for L4CFG and WKUPAON clockdomains.
Without this the DCAN1 RAMINIT.DONE bit never gets set after the
RAMINIT start sequence.

Signed-off-by: Roger Quadros <rogerq@ti.com>
ARM: dts: dra7-evm: Keep all VDD rails always-on

DRA7 Data Manual (SPRS857L - August 2014) section 4.1.1 states: "All
unused power supply balls must be supplied with the voltages specified
in the Section 5.2, Recommended Operating Conditions".

This implies that all unused voltage rails for Vayu can never be
switched off even if the hardware blocks inside that voltage domain is
unused. Switching off these unused rails may result in stability issues
on other domains and increased leakage and power-on-hour impacts.

J6eco-evm dts file already considers this, however j6evm-dts file needs
to be fixed to consider this constraint of the SoC.

Signed-off-by: Nishanth Menon <nm@ti.com>
pinctrl: dra: dt-bindings: Fix output pull up/down

For PIN_OUTPUT_PULLUP and PIN_OUTPUT_PULLDOWN we must not set the
PULL_DIS bit which disables the PULLs.

PULL_ENA is a 0 and using it in an OR operation is a NOP, so don't
use it in the PIN_OUTPUT_PULLUP/DOWN macros.

Fixes: 23d9cec07c58 ("pinctrl: dra: dt-bindings: Fix pull enable/disable")

Signed-off-by: Roger Quadros <rogerq@ti.com>