Add folding rules for: Sar64(x,0) and Sar32(x,0).  Immediate
shifts by zero seem to have a surprisingly large perf hit on
Intels, possibly due to the bizarre eflags/rflags semantics
involved.



git-svn-id: svn://svn.valgrind.org/vex@2964 8f6e269a-dfd6-0310-a8e1-e2731360e62c
guest_amd64_spechelper: fill in a number of missing cases for
conditions after SUBQ/SUBL/SUBW.  Also, add cases for
Overflow-after-ADDL/SUBL for the benefit of code generated by
Javascript JITs.



git-svn-id: svn://svn.valgrind.org/vex@2965 8f6e269a-dfd6-0310-a8e1-e2731360e62c