i#1551 port to ARM: encode GPR register lists

Adds encoding for GPR register lists.
The strategy is to greedily consume all GPR's in the operand sequence when
a register list type is encountered, recording the start and endpoints.  If
the subsequent type is a plain GPR, and the list had more than one
register, the final register is peeled off from the list and assigned to
the plain GPR.

This only works with only one register list per template (already required
on decoding) and at most one plain reg immediately following a register
list type.  Our new previously-committed decoder debug checks ensure this
for us.

Adds OPND_CREATE_MEMLIST().

Still TODO: add SIMD register list encoding support.
i#1551 port to ARM: OP_vtbl and OP_vtbx register lists

Adds new types TYPE_L_VAx{2,3,4} for OP_vtbl and OP_vtbx.
i#1551 port to ARM: OP_vtb{l,x} decoding

Adds a new table to properly decode OP_vtb{l,x} whose use of VA thwarts the
prior decoding sequence.

Removes the incorrect VA from OP_vcl{s,z}.
i#1551 port to ARM: decoding of memory before reglist

When decoding, we now get the memory access size right when it precedes its
corresponding reglist operand.

Adds missing size names for disassembly suffixes for register-list-sized
memory accesses.