Merge atse(4) interrupt handling and race condition fixes from cheribsd:

commit 8bd88585ed8e3f7def0d780a1bc30d96fe642b9c

    Rework atse_rx_cycles handling: count packets instead of fills, and use the
    limit only when polling, not when in interrupt mode.  Otherwise, we may
    stop reading the FIFO midpacket and clear the event mask even though the
    FIFO still has data to read, which could stall receive when a large packet
    arrives.  Add a comment about races in the Altera FIFO interface: we may
    need to do a little more work to handle races than we are.

commit 20b39086cc612f8874dc9e6ef4c0c2eb777ba92a

    Use 'sizeof(data)' rather than '4' when checking an mbuf bound, as is the
    case for adjusting length/etc.

commit e18953174a265f40e9ba60d76af7d288927f5382

    Break out atse_intr() into two separate routines, one for each of the two
    interrupt sources: receive and transmit.

commit 6deedb43246ab3f9f597918361831fbab7fac4ce

    For the RX interrupt, take interest only in ALMOSTEMPTY and OVERFLOW.
    For the TX interrupt, take interest only in ALMOSTFULL and UNDERFLOW.

    Perform TX atse_start_locked() once rather than twice in TX interrupt
    handling -- and only if !FULL, rather than unconditionally.

commit 12601972ba08d4380201a74f5b967bdaeb23092c

    Experimentation suggests that the Altera Triple-Speed Ethernet documentation
    is incorrect and bits in the event and interrupt-enable registers are not
    irrationally rearranged relative to the status register.

commit 3cff2ffad769289fce3a728152e7be09405385d8

    Substantially rework interrupt handling in the atse(4) driver:

    - Introduce a new macro ATSE_TX_PENDING() which checks whether there is
      any pending data to transmit, either in an in-progress packet or in
      the TX queue.
    - Introduce new ATSE_RX_STATUS_READ() and ATSE_TX_STAUTS_WRITE() macros
      that query the FIFO status registers rather than event registers,
      offering level- rather than edge-triggered FIFO conditions.
    - For RX, interrupt only on full/overflow/underflow; for TX, interrupt
      only on empty/overflow/underflow.
    - Add new ATSE_RX_INTR_READ() and ATSE_RX_INTR_WRITE() macros useful for
      debugging interrupt behaviour.
    - Add a debug.atse_intr_debug_enable sysctl that causes various pieces
      of FIFO state to be printed out on each RX or TX interrupt.  This is
      disabled by default but good to turn on if the interface appears to
      wedge.  Also print debugging information when polling.
    - In the watchdog handler, do receive, not just transmit, processing, to
      ensure that the rx, not just tx, queue is being handled -- and, in
      particular, will be drained such that interrupts can resume.
    - Rework both atse_rx_intr() and atse_tx_intr() to eliminate many race
      conditions, and add comments on why various things are in various
      orders.  Interactions between modifications to the event and interrupt
      masks are quite subtle indeed, and we must actively check for a number
      of races (e.g., event mask cleared; packet arrives; interrupts enabled).
      We also now use the status registers rather than event registers for
      FIFO status checks to avoid other races; we continue to use event
      registers for underflow/overflow.

    With this change, interrupt-driven operation of atse appears (for the
    time being) robust.

commit 3393bbff5c68a4e61699f9b4a62af5d2a5f918f8

    atse: Fix build after 3cff2ffa

Obtained from:	cheribsd
Submitted by:	rwatson, emaste
Sponsored by:	DARPA/AFRL
MFC after:	3 days