hdl/modules/*: add deswitching clk to position_calc_core module
hdl/modules/wb_un_cross/wbgen/*: (1/5) update wbgen files

Add switching clock output enable. This effectively
starts the switch counter from 0 to the max value.
This is necessary as the RFFE controller needs to
be in a known state before the first switching clock
edge.

This is accomplished by disabling the switching clock,
commanding the RFFE controller to the direct switch state
and then enabling the switching clock
hdl/modules/wb_un_cross/*: (2/5) add switching clock enable input

Use switching clock enable in the clock generation logic
hdl/modules/sw_windowing: (3/5) add switching clock enable input

Use switching clock enable in the clock generation logic
hdl/modules/wb_position_calc_core/*: (4/5) add switching clock enable input

Use switching clock enable in the clock generation logic
hdl/modules/dsp_cores_pkg.vhd: (5/5) update all modules definitions

Use switching clock enable in the clock generation logic