[PowerPC] Fix readcyclecounter to be custom expanded for all 32-bit targets

We need to use the custom expansion of readcyclecounter on all 32-bit targets
(even those with 64-bit registers). This should fix the ppc64 buildbot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223182 91177308-0d34-0410-b5e6-96231b3b80d8
[MCJIT] Unique-ptrify the RTDyldMemoryManager member of MCJIT. NFC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223183 91177308-0d34-0410-b5e6-96231b3b80d8
[X86][MC] Intel syntax: accept implicit memory operand sizes larger than 80.

The X86AsmParser intel handling was refactored in r216481, making it
try each different memory operand size to see which one matches.
Operand sizes larger than 80 ("[xyz]mmword ptr") were forgotten, which
led to an "invalid operand" error for code such as:
  movdqa [rax], xmm0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223187 91177308-0d34-0410-b5e6-96231b3b80d8
ExceptionDemo: Let setMCJITMemoryManager() take unique_ptr, since r223183.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223188 91177308-0d34-0410-b5e6-96231b3b80d8
Prologue support

Patch by Ben Gamari!

This redefines the `prefix` attribute introduced previously and
introduces a `prologue` attribute.  There are a two primary usecases
that these attributes aim to serve,

  1. Function prologue sigils

  2. Function hot-patching: Enable the user to insert `nop` operations
     at the beginning of the function which can later be safely replaced
     with a call to some instrumentation facility

  3. Runtime metadata: Allow a compiler to insert data for use by the
     runtime during execution. GHC is one example of a compiler that
     needs this functionality for its tables-next-to-code functionality.

Previously `prefix` served cases (1) and (2) quite well by allowing the user
to introduce arbitrary data at the entrypoint but before the function
body. Case (3), however, was poorly handled by this approach as it
required that prefix data was valid executable code.

Here we redefine the notion of prefix data to instead be data which
occurs immediately before the function entrypoint (i.e. the symbol
address). Since prefix data now occurs before the function entrypoint,
there is no need for the data to be valid code.

The previous notion of prefix data now goes under the name "prologue
data" to emphasize its duality with the function epilogue.

The intention here is to handle cases (1) and (2) with prologue data and
case (3) with prefix data.

References
----------

This idea arose out of discussions[1] with Reid Kleckner in response to a
proposal to introduce the notion of symbol offsets to enable handling of
case (3).

[1] http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-May/073235.html

Test Plan: testsuite

Differential Revision: http://reviews.llvm.org/D6454

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223189 91177308-0d34-0410-b5e6-96231b3b80d8
GCRelocateOperands: Try to appease msc17.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223192 91177308-0d34-0410-b5e6-96231b3b80d8
Emit the entry block first and the exit block second, then all the blocks in between afterwards. This is what gcc always does, and some out of tree tools depend on that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223193 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Change mubuf offsets to print as decimal

This matches SC's behavior.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223194 91177308-0d34-0410-b5e6-96231b3b80d8
[OCaml] [cmake] Disable OCaml bindings if ctypes >=0.3 is not found.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223195 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Enable inline assembly

We just needed to remove the assertion in
AMDGPURegisterInfo::getFrameRegister(), which is called when
initializing the parser for inline assembly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223197 91177308-0d34-0410-b5e6-96231b3b80d8
NVPTX: Delete dead code

`MDNode` does not inherit from `User`, and it never has a name.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223198 91177308-0d34-0410-b5e6-96231b3b80d8
StructurizeCFG: Use LoopInfo analysis for better loop detection

We were assuming that each back-edge in a region represented a unique
loop, which is not always the case.  We need to use LoopInfo to
correctly determine which back-edges are loops.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223199 91177308-0d34-0410-b5e6-96231b3b80d8
ADT: Add SmallVector<>::emplace_back()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223201 91177308-0d34-0410-b5e6-96231b3b80d8
ADT: Add SmallVector<>::emplace_back(): fixup

Add missing `void` return type from `!LLVM_HAS_VARIADIC_TEMPLATES` case
in r223201.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223202 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Fix live range error hidden by SIFoldOperands

m0 is treated as a virtual register class with a single register
rather than the physical register it really is. This was updating
the live range of the used virtual copy of m0 from the first ds_read
instruction, and leaving the unused copy unchanged. This resulted in a
"Live segment doesn't end at a valid instruction" verifier error because
the erased instructions. Update the live range of the second copy (which
should be dead).

No test since I'm not sure how to trigger this with SIFoldOperands
enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223203 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Fix running SILowerI1Copies a second time

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223204 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Fix suspicious indexing

The loop is over the operands of an instruction, and checks the
register with the sub reg index of the dest register. This probably
meant to be checking the sub reg index of the same operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223205 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Remove i1 pseudo VALU ops

Select i1 logical ops directly to 64-bit SALU instructions.
Vector i1 values are always really in SGPRs, with each
bit for each item in the wave. This saves about 4 instructions
when and/or/xoring any condition, and also helps write conditions
that need to be passed in vcc.

This should work correctly now that the SGPR live range
fixing pass works. More work is needed to eliminate the VReg_1
pseudo regclass and possibly the entire SILowerI1Copies pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223206 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Remove incorrect assertion

This can be a COPY to a physical register, such as VCC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223207 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Fix SIFixSGPRCopies for copies to physical registers

This shows up when operands required to be passed in VCC are copied
to.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223208 91177308-0d34-0410-b5e6-96231b3b80d8