Removed line in Vec.scala to not generate ROMs, because it breaks verilog
Merge branch 'master' into dse
Added flags to call Params.dump and Params.load from chiselMain
Fixed mismatched type issue
Fixed misspelling of 'flattenning'
Relocated jackhammer functions into chisel
Added Jackhammer.scala to implement jackhammer functionality, including dumping and loading .prm files
Merge branch 'master' of https://github.com/ucb-bar/chisel into dse

Conflicts:
	src/main/scala/Vec.scala
A large commit:
 -Added oscar lib for constraint solving for Jackhammer
 -Refactored Jackhammer to plug into oscar
 -Refactored Param classes to enable constraints between parameters
 -Changed serialization and deserialization to work with new parameters
Cleaned up filename of design.prm files
Merge branch 'master' of github.com:ucb-bar/chisel into dse
Eliminate global when, switch stacks

This supports instantiation of modules within when statements.  Note
this is not conditional instantiation, which does not make sense. It
is equivalent to instantiating a module outside of the when statement.
update to docs for dsp bootcamp
Some fixes and comments in getting started
Catch remaining param classes for cpp generation
Merge branch 'master' of github.com:ucb-bar/chisel into dse
Merge pull request #132 from schoeberl/master

Some fixes and comments in getting started
Fix Verilog backend regression introduced in f6bee8a4d930b613262addac8af91ed57ab1c329
check for assigning to non port inputs and make sure all module io are ports

Conflicts:

	src/main/scala/Bits.scala
	src/test/scala/DataTest.scala
merge