rtl/cache: don't drive d_data when we do a read bypass.

Now that we have a shared read/write data bus we don't want to drive
d_data unless we're actually reading.
verif: provide a fast UART for simulations.

The back-to-back UART gives the best verification - it models more of
the SoC, but at 115,200 baud it means I/O is too slow to be useful.