- init Repo
add Readme
add Readme
add simple Sequencer
rename Recorder --> Storage
add Recorder
add Trigger
fix masks on EdgeDetector
simplify EdgeDetector
add register interface to Trigger
new library spi2Csr (skeleton)
Add simulation skeleton
Remove SRLC16E, will be replaced by distributed ram
use ram for Sum
add sim: tb_TriggerCsr.py
add sim: tb_Spi2Csr.py (skeleton, WIP)
- fix Spi2Csr mistakes
tb_spi2Csr: Add clk_ratio
tb_spi2Csr: Add Read
spi2Csr : fixs
add truth table generator
tb_TriggerCsr.py : use truth table generator for Sum Lut
add vcd generator
split migScope to trigger & recorder