hdl/modules/pcie/*/DDRs_Control.vhd: fix vector size for Virtex6
bpm_pcie_ml605.vhd: comment out signals and fix addr vector
emb-sw/*: generate ramp test data
hdl/ml_605/dbe_bpm_fmc130m_4ch_pcie/*: test PCIe integration
hdl/syn/*/dbe_bpm_fmc130m_4ch_pcie/*: new syn files for PCIe integration
hdl/ip_cores/dsp-cores: update submodule reference
hdl/ml_605/dbe_bpm_dsp_fmc130m_4ch/*: update chipscope project
hdl/syn/ml605/dbe_bpm_dsp_fmc130m_4ch/*: update and clean syn files
hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/*: update ucf for dsp-cores

This was copied verbatim as located in dsp-cores
repository commit 023e0c7c76
hdl/top/ml_605/dbe_bpm_dsp_fmc130m_4ch/*: update chipscope projects
Merge branch 'master' into pcie-test
hdl/platform/virtex6/*: add chipscope 6 port
hdl/modules/*/wb_acq_core/*: (1/5) add data acquisition module

This module allows storage of samples from a streaming data source
on the following modes:

1) Simple acquisition on request
2) Pre-trigger acquisition
3) Post-trigger acquisition
4) Pre+Post-trigger acquisition

Also, two acquisition variations are possible:

1) Single-shot (one time) acquisition
2) Multi-shot (multiple times) acquisition

There are a lot of improvements and fixes to be done!
This is work in progress!

The design was partially based on the original HDL module
fmc_adc_100Ms_core from the fmc-adc-100m ohwr repository
(http://www.ohwr.org/projects/fmc-adc-100m14b4cha/repository)
hdl/modules/dbe_wishbone/*: (2/5) add data acquisition module

Add wishbone top modules to the central dbe_wishbone_pkg
package
hdl/modules/dbe_wishbone/*: (3/5) add data acquisition module

Add "wb_acq_core" folder module to the Manifest file
hdl/sim/regs/*: (4/5) add data acquisition module

Add simulation register definitions
hdl/testbench/*/wb_acq_core_test/*: (5/5) add data acquisition module

Add testbenches for the acquisition module
hdl/top/pcie/bpm_pcie_ml605.vhd: comment out signals

This was necessary, in order to use an external set
of DDR3 UI signals
hdl/platform/*/Manifest.py: fix wrong pathname
hdl/top/ml_605/dbe_bpm_fmc130m_4ch_pcie/*: add wb_acq_core module

This commit adds the data acquisition core to the pcie design
to demonstrate DMA read/write from the SDRAM