mm: Fix incorrect cache attribute restoration.

armv7 uses cache policy as WRITEALLOC. CPA is
restoring the cache attributes to WRITEBACK during
set_pages_array_wb().
Fixed issues in pmd to pte prot translation and vice versa.

Change-Id: I8406b784f62d559f657ef7bc08e77c83ac6e5690
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/122472
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
mm: Avoid freeing init and initrd memory when CPA is enabled.

Align memblock reserve for text area to PMD size.
Reserve the memory hole between DRAM start and Page table start.
Add Sanity check to avoid section split in text area.

Bug 1028787

Change-Id: I586e4ad6e3a94aa0c79b302e51156dbe089e481f
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/121883
(cherry picked from commit 65d02640b4b0b38263687c7f3e664c873237dc43)
Reviewed-on: http://git-master/r/123431
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
video: tegra: host: Fix leak in 3D register read

When 3D register is read, and we need to do a context switch, the old
context reference is incremented, but it never gets decremented. Fix
by using nvhost_job_get_hwctx() to acquire the reference.

Bug 1031746

Change-Id: Ic72637cb2399f960e2297733bfe45e585a8ec180
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/123678
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
GVS: Gerrit_Virtual_Submit
video: tegra: host: Fix crash if allocation fails

nvhost_module_remove_client assumes that a client structure
to be freed exists in the linked list. However, if an allocation fails
in nvhost_module_add_client, no client structure is allocated, and
during cleanup, nvhost_module_remove_client would then attempt
to free an invalid pointer.

Bug 1034729

Change-Id: Ie1a641071b86f8246951e9be824a6003f14b04b6
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Reviewed-on: http://git-master/r/124096
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
video: tegra: cardhu: Default bpp from hardware

This patch adds:

1. A kernel config option that hints to DC driver
to use the current value of the color depth
register as the default for initializing the FB
driver.

2. Checks to see if DC is enabled before reading
off the color depth register in tegra_dc_probe.

Change-Id: I852cc1328fcf42f33052f46b86d753e691744329
Signed-off-by: Christopher Freeman <cfreeman@nvidia.com>
Reviewed-on: http://git-master/r/127297
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
Signed-off-by: revjunkie <rajibrahim@rocketmail.com>