Allow ignored blocks to take multiple lines

The VCD files that are output by VCS contain blocks that I don't care
about but that span multiple lines.  This deals with that sort of
output.
Allow "reg" or "wire" variables interchangeably

I have no idea what the difference between these two are, but
apparently VCS outputs "reg" type variables sometimes.  I've actually
seen Chisel do this as well...

Who knows.
Ignore "$date" blocks
Skip "$version" blocks
Skip blank lines
Add a missing "static"
Print the VCD line number on failures

This maks tracking down parse failures a whole lot easier: this way I
can find the failing line a whole lot quicker.
Skip "$dumpvars" blocks in the clock half

I have no idea what's going on here, but for some reason it appears
that VCS wraps the first block of values in a "$dumpvars" block.  As
far as I can tell it doesn't do anything, so I'm just ignoring it.
Handle VCS's special 1-bit wire syntax
Show the diff before the return in the harness

This lets me see _why_ a test is failing before just seeing that it
fails.
Handle having multiple long names with one short name

So I have no idea what's going on here, but VCS appears to sometimes
output some signals with the same short name and expect that this
applies to all the long names.  I fixed this in a somewhat ineffecient
way: just copy the output to all the long names.

For now, I guess it works.