First pass at the receiver.

* Added in ADC pins.
* Script to control a receive in lib/app
* CMX991 receive API includes picking IFIP[1,2] pin
First pass at the HDL for the receiver.

* Add receive to the apb3 master mock.
* Implement a receiver which buffers samples.
* Fails simulation b/c no resampling yet.
Decimate on receive.

* Added decimation and throttling.
* Simulation runs for 50ms.
* Fixed FIFO flag bug.
* Added APB3 delay.
Receiver decimates and processing program runs forever.

* Implement a simple Direct Digital Synthesizer with a LUT
* Fix bugs in the FIFO and reset circuitry.
* Decimate 10e9 S/s to 50e3 S/s and get it from the FPGA to the ARM processor
  (in simulation only.)
Flesh out exciter to stream samples or be DDS.

* Updated Exciter to be a proper DUC DSP flow
* HDL fixed for APB3, DDS, and FIFO
* Commands for doing CW and streaming samples.
* Added a way to graph samples coming out of GNURadio
* Updated to emcraft-linux-cortexm-0.11
Library
HDL
Driver
Docs.
Add modprobe boot of whitebox device & remote serial test suite.
Forgot modules.dep.
Refactored ring_buffer into user_source / rf_sink.
Exciter / Mock-Exciter abstraction.

* Add module sysfs switch to choose mock or regluar exciter.
* Automatically use the mock for the driver tests.
Half-duplex driver state machine.

* Using sysfs module params as ABI to test_driver
* TXSTOP is the halt symbol for the transmitter
* Mock exciter implementation
Driver watches overruns / underruns.

* Check for overrun or underrun in read / write / fsync.
* Add end-to-end test for read and write (fails.)
Refactor tx to file.

This will make writing rx easier.
Driver for the receiver.

* RF source / User sink blocks.
* Driver read f_op.
* Mock exciter and receiver share circular buffer.
* End-to-end tests pass for the mock.
Fix device level tests & lock-check ioctl.
Update exciter to drop-in to new driver.

* Can flip easily between mock for testing and actual HDL via
  /sys/modules/whitebox/parameters/whitebox_mock_en
* Added WES_TXSTOP, and the cascading path of this signal to the
  DAC.
* Added tests in both simulation and on the programmed device to
  check that the TXSTOP works.
Synchronizing HDL

* On the path to timing closure; I've buffered most of the control
  lines across clock domains.
* Still to do: reset module, dac_clock/dac_2xclock phase constraint
* New duc_enable flag lets you turn off including the Digital Up
  Converter DSP from the final verilog output.
* New simple APB3 slave and simulation.  Testing on device also a TODO.