Add extra new line and remove some trailing whitespace from tablegen RegisterInfo output file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222508 91177308-0d34-0410-b5e6-96231b3b80d8
Remove a bunch of unnecessary typecasts to 'const TargetRegisterClass *'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222509 91177308-0d34-0410-b5e6-96231b3b80d8
DAGCombiner: Allow the DAGCombiner to combine multiple FDIVs with the same divisor info FMULs by the reciprocal.
E.g., ( a / D; b / D ) -> ( recip = 1.0 / D; a * recip; b * recip)

A hook is added to allow the target to control whether it needs to do such combine.

Reviewed in http://reviews.llvm.org/D6334


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222510 91177308-0d34-0410-b5e6-96231b3b80d8
Add LLVMScalarOpts to LLVMPowerPCCodeGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222516 91177308-0d34-0410-b5e6-96231b3b80d8
[asan] Add new hidden compile-time flag asan-instrument-allocas to sanitize variable-sized dynamic allocas. Patch by Max Ostapenko.

Reviewed at http://reviews.llvm.org/D6055


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222519 91177308-0d34-0410-b5e6-96231b3b80d8
[X86] For Silvermont CPU use 16-bit division instead of 64-bit for small positive numbers

Differential Revision: http://reviews.llvm.org/D5938



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222521 91177308-0d34-0410-b5e6-96231b3b80d8
[DAG] Refactor the shuffle combining logic in DAGCombiner. NFC.

This patch simplifies the logic that combines a pair of shuffle nodes into
a single shuffle if there is a legal mask. Also added comments to better
describe the algorithm. No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222522 91177308-0d34-0410-b5e6-96231b3b80d8
[x86] Add a bunch of test cases to 256-bit shuffles that exercise
merging 128-bit subvectors and also shuffling all the elements of those
subvectors. Currently we generate pretty bad code for many of these, but
I'm testing a patch that should dramatically improve this in addition to
making the shuffle lowering robust to other changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222525 91177308-0d34-0410-b5e6-96231b3b80d8
[x86] Remove more windows line endings that slipped into this file...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222528 91177308-0d34-0410-b5e6-96231b3b80d8
[x86] Teach the x86 vector shuffle lowering to detect mergable 128-bit
lanes.

By special casing these we can often either reduce the total number of
shuffles significantly or reduce the number of (high latency on Haswell)
AVX2 shuffles that potentially cross 128-bit lanes. Even when these
don't actually cross lanes, they have much higher latency to support
that. Doing two of them and a blend is worse than doing a single insert
across the 128-bit lanes to blend and then doing a single interleaved
shuffle.

While this seems like a narrow case, it kept cropping up on me and the
difference is *huge* as you can see in many of the test cases. I first
hit this trying to perfectly fix the interleaving shuffle patterns used
by Halide for AVX2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222533 91177308-0d34-0410-b5e6-96231b3b80d8
[DAG] Teach how to turn a build_vector into a shuffle if some of the operands are zero.

Before this patch, the DAGCombiner only tried to convert build_vector dag nodes
into shuffles if all operands were either extract_vector_elt or undef.

This patch improves that logic and teaches the DAGCombiner how to deal with
build_vector dag nodes where one or more operands are zero. A build_vector
dag node with some zero operands is turned into a shuffle only if the resulting
shuffle mask is legal for the target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222536 91177308-0d34-0410-b5e6-96231b3b80d8
[x86] Make the previous logic significantly less conservative and get
a bunch more improvements.

Non-lane-crossing is fine, the key is that lane merging only makes sense
for single-input shuffles. Not sure why I got so turned around here. The
code all works, I was just using the wrong model for it.

This only updates v4 and v8 lowering. The v16 and v32 lowering requires
restructuring the entire check sequence.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222537 91177308-0d34-0410-b5e6-96231b3b80d8
Allow FDE references outside the +/-2GB range supported by PC relative
offsets for code models other than small/medium. For JIT application,
memory layout is less controlled and can result in truncations
otherwise. 

Patch from Akos Kiss.

Differential Revision: http://reviews.llvm.org/D6079


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222538 91177308-0d34-0410-b5e6-96231b3b80d8
[x86] Restructure the checking patterns for v16 and v32 avx2 vector
shuffle lowering to allow much better blend matching.

Specifically, with the new structure the code seems clearer to me and we
correctly can hit the cases where merging two 128-bit lanes is a clear
win and can be shuffled cheaply afterward.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222539 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "Allow FDE references outside the +/-2GB range supported by PC relative offsets for code models other than small/medium. For JIT application, memory layout is less controlled and can result in truncations otherwise."

This reverts commit r222538.

It's causing test failures for CFI, at least on Darwin:

http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental/1189/
http://lab.llvm.org:8080/green/job/clang-stage1-configure-RA_check/1391/

Note that the previous incremental build was on r222537, and the CFI
tests weren't failing:
http://lab.llvm.org:8080/green/job/clang-stage1-cmake-RA-incremental/1188/

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222542 91177308-0d34-0410-b5e6-96231b3b80d8
Add a feature flag for slow 32-byte unaligned memory accesses [x86].

This patch adds a feature flag to avoid unaligned 32-byte load/store AVX codegen
for Sandy Bridge and Ivy Bridge. There is no functionality change intended for 
those chips. Previously, the absence of AVX2 was being used as a proxy to detect
this feature. But that hindered codegen for AVX-enabled AMD chips such as btver2
that do not have the 32-byte unaligned access slowdown.

Performance measurements are included in PR21541 ( http://llvm.org/bugs/show_bug.cgi?id=21541 ).

Differential Revision: http://reviews.llvm.org/D6355



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222544 91177308-0d34-0410-b5e6-96231b3b80d8
Fix formatting. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222545 91177308-0d34-0410-b5e6-96231b3b80d8
Less space; NFC


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222546 91177308-0d34-0410-b5e6-96231b3b80d8
Allow multiple -debug-only args

Debug output is shown if any of the -debug-only arguments match.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222547 91177308-0d34-0410-b5e6-96231b3b80d8
Add and use a helper elements() to StructType. NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222553 91177308-0d34-0410-b5e6-96231b3b80d8