Lots of change. 1, connect CPU and UART through MemMap; there is one UART at CPU side, another UART at testbench. 2, fix parameter ClockFreq to 50_000_000 in EchoTestbench.v, UART.v, UATransmit.v and UAReceive.v. 3, the echo.c.llvm.s contains '.set noreorder' and it prevents compiler generating delay slot for lw. Wrote a perl script to remove '.set noreorder' in Makefile. 4, sb and sh do not work correctly, add StoreData module to fix the problem. Finally, EchoTestbench is simulated sucessfully!