Use GateGenerator for PID/RefTDC L1 output. Disadvantage: Minimum Width=2, Advantages: No glitch an trailing edge (firmware 7e), jitter-free gate width for PID
Improved but not perfect GateGenerator. Synced version is still one clock cycle longer in roughly 0.1% of the cases...
Merge pull request #2 from neiser/master

Firmware 7e, better but not perfect PID gate