Merged pull request 271
Removed exit statement from test.tcl
Updated commit_id for junit & diff for 2014.3
Merge pull request #272 from dpefour/master

Merged pull request 271 and updated 2014.3 catalog for diff/junit
Major updates to insert_buffer.tcl
Minor updates to the metacomments
Update 2014.3 catalog for latest changes in designutils
Merge pull request #273 from dpefour/master

Major updates to insert_buffer.tcl
- write native compile script for ModelSim
Automated update of XilinxTclStore by processTclStoreSubmit.pl on 20140626103024. Submit user: rajklair, branch: master.
cr:943632 - fixed verilog_define propagation issue
Automated update of XilinxTclStore by processTclStoreSubmit.pl on 20140626160929. Submit user: rajklair, branch: master.
805342 - do not sort compile order for verilog and vhdl (default behavior)
Merge branch 'master' of http://github.com/rajklair/XilinxTclStore into rajklair-master
Automated update of XilinxTclStore by processTclStoreSubmit.pl on 20140626171055. Submit user: rajklair, branch: master.
fixed msg format (send_msg_id)
Automated update of XilinxTclStore by processTclStoreSubmit.pl on 20140627082438. Submit user: rajklair, branch: master.
merging upstream changes