hdl/modules/wb_un_cross/*: add registered ouput

The status signal of swap_cnt_top was unregistered.
So, we do it here and upadte the additional clock latency
on wb_position_calc_core
models/*: (1/3) use 560 CE instead of 1120 for FOFB CORDIC

This would give an additional ADC clock cycle for
timing slack, easing the timing closure
hdl/modules/*/generated/virtex6/*: (2/3) use 560 CE instead of 1120 for FOFB CORDIC

This would give an additional ADC clock cycle for
timing slack, easing the timing closure
hdl/modules/*/generated/artix7/*: (3/3) use 560 CE instead of 1120 for FOFB CORDIC

This would give an additional ADC clock cycle for
timing slack, easing the timing closure