Introduce CPUStringIsValid() into MCSubtargetInfo and use it for ARM .cpu parsing.

Previously .cpu directive in ARM assembler didnt switch to the new CPU and
therefore acted as a nop. This implemented real action for .cpu and eg. 
allows to assembler FreeBSD kernel with -integrated-as.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223147 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Fix passing of small structures for big-endian O32.

Summary:
Like N32/N64, they must be passed in the upper bits of the register.

The new code could be merged with the existing if-statements but I've
refrained from doing this since it will make porting the O32 implementation
to tablegen harder later.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6463


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223148 91177308-0d34-0410-b5e6-96231b3b80d8
Restructure some assertion checking based on post commit feedback by Aaron and Tom.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223150 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Cleanup some tests and add missing testcases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223151 91177308-0d34-0410-b5e6-96231b3b80d8
Add bindings for the rest of the MCJIT options that we previously
had support for. We're still missing a binding for an MCJIT
memory manager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223153 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Move more information into SIProgramInfo struct

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223154 91177308-0d34-0410-b5e6-96231b3b80d8
[AArch64][Stackmaps] Optimize stackmap shadows on AArch64.

Reduce the number of nops emitted for stackmap shadows on AArch64 by counting
non-stackmap instructions up to the next branch target towards the requested
shadow.

<rdar://problem/14959522>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223156 91177308-0d34-0410-b5e6-96231b3b80d8
Make sure that the TargetOptions operator== is checking the
full contents of the class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223159 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: Emit amd_kernel_code_t header for AMDGPU environment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223160 91177308-0d34-0410-b5e6-96231b3b80d8
[PowerPC] Implement readcyclecounter for PPC32

We've long supported readcyclecounter on PPC64, but it is easier there (the
read of the 64-bit time-base register can be accomplished via a single
instruction). This now provides an implementation for PPC32 as well. On PPC32,
the time-base register is still 64 bits, but can only be read 32 bits at a time
via two separate SPRs. The ISA manual explains how to do this properly (it
involves re-reading the upper bits and looping if the counter has wrapped while
being read).

This requires PPC to implement a custom integer splitting legalization for the
READCYCLECOUNTER node, turning it into a target-specific SDAG node, which then
gets turned into a pseudo-instruction, which is then expanded to the necessary
sequence (which has three SPR reads, the comparison and the branch).

Thanks to Paul Hargrove for pointing out to me that this was still unimplemented.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223161 91177308-0d34-0410-b5e6-96231b3b80d8
Give lit a --xunit-xml-output option for saving results in xunit format
  
  --xunit-xml-output saves test results to disk in JUnit's xml format. This will allow Jenkins to report the details of a lit run.
  
  Based on a patch by David Chisnall.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223163 91177308-0d34-0410-b5e6-96231b3b80d8
[X86][SSE] Keep 4i32 vector insertions in integer domain on SSE4.1 targets

4i32 shuffles for single insertions into zero vectors lowers to X86vzmovl which was using (v)blendps - causing domain switch stalls. This patch fixes this by using (v)pblendw instead.

The updated tests on test/CodeGen/X86/sse41.ll still contain a domain stall due to the use of insertps - I'm looking at fixing this in a future patch.

Differential Revision: http://reviews.llvm.org/D6458



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223165 91177308-0d34-0410-b5e6-96231b3b80d8
Apply loop-rotate to several vectorizer tests.

Such loops shouldn't be vectorized due to the loops form.
After applying loop-rotate (+simplifycfg) the tests again start to check
what they are intended to check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223170 91177308-0d34-0410-b5e6-96231b3b80d8
PR21302. Vectorize only bottom-tested loops.

rdar://problem/18886083

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223171 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: don't be too greedy when folding :lo12: accesses into mem ops.

This frequently leads to cases like:
   ldr xD, [xN, :lo12:var]
   add xA, xN, :lo12:var
   ldr xD, [xA, #8]

where the ADD would have been needed anyway, and the two distinct addressing
modes can prevent the formation of an ldp. Because of how we handle ADRP
(aggressively forming an ADRP/ADD pseudo-inst at ISel time), this pattern also
results in duplicated ADRP instructions (one on its own to cover the ldr, and
one combined with the add).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223172 91177308-0d34-0410-b5e6-96231b3b80d8
Use a typed enum instead of 'unsigned char' for packed field.  NFC.

This makes it easier to debug Twine as the 'Kind' fields now show their enum values in lldb and not escaped characters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223178 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: strengthen Darwin ABI alignment assumptions

A global variable without an explicit alignment specified should be assumed to
be ABI-aligned according to its type, like on other platforms. This allows us
to use better memory operations when accessing it.

rdar://18533701

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223180 91177308-0d34-0410-b5e6-96231b3b80d8
[PowerPC] Fix readcyclecounter to be custom expanded for all 32-bit targets

We need to use the custom expansion of readcyclecounter on all 32-bit targets
(even those with 64-bit registers). This should fix the ppc64 buildbot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223182 91177308-0d34-0410-b5e6-96231b3b80d8
[MCJIT] Unique-ptrify the RTDyldMemoryManager member of MCJIT. NFC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223183 91177308-0d34-0410-b5e6-96231b3b80d8
[X86][MC] Intel syntax: accept implicit memory operand sizes larger than 80.

The X86AsmParser intel handling was refactored in r216481, making it
try each different memory operand size to see which one matches.
Operand sizes larger than 80 ("[xyz]mmword ptr") were forgotten, which
led to an "invalid operand" error for code such as:
  movdqa [rax], xmm0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223187 91177308-0d34-0410-b5e6-96231b3b80d8