defconfigs: Enable ARCH_Random

Currently, the software random number generator is not intialized
until relatively late in the boot process. Software that relies on
random numbers early will not be reliable. Entropy sources are
available early but not early enough for some use cases which means
that moving the software random number generation earlier is not an
option. As an alternate solution, implement the functions associated
with CONFIG_ARCH_RANDOM. These functions currently make a call into
trustzone to get reliable random numbers. The functions are disabled
once the regular random number generator is sufficiently reliable.
boost volume
add BadAss CPU gov

Conflicts:
	drivers/cpufreq/Kconfig
	drivers/cpufreq/Makefile
add danca dance cpu governor

Conflicts:
	drivers/cpufreq/Kconfig
GPU: Increase bandwidth
add lionheart cpu gov

Also fix Makefile

Conflicts:
	drivers/cpufreq/Makefile
cpufreq: intelliactive: initial coding and introduction!

intelliactive is based on Latest Google Interactive cpufreq governor from
Google.  The original Interactive provides smooth UI operations but suffers
slight battery drain due to its aggressive policies.  Intelliactive is an
improvement built on top of it.

It has the following enhancements added:
1. self-boost capability from input drivers (no need for PowerHAL assist)
2. two phase scheduling (idle/busy phases to prevent from jumping directly to
   max freq
3. Checks for offline cpus and short circuits some unnecessary checks to
   improve code execution paths
4. removed trace calls

Signed-off-by: Paul Reioux <reioux@gmail.com>

Conflicts:
	drivers/cpufreq/Kconfig
	drivers/cpufreq/Makefile
	include/linux/cpufreq.h
intelliactive: tune for APQ8064 devices

Signed-off-by: Paul Reioux <reioux@gmail.com>
intelliactive: fix race condition when unregistering input handlers

Signed-off-by: Paul Reioux <reioux@gmail.com>
IntelliDemand 5.0
ARM: 7587/1: implement optimized percpu variable access

Use the previously unused TPIDRPRW register to store percpu offsets.
TPIDRPRW is only accessible in PL1, so it can only be used in the kernel.

This replaces 2 loads with a mrc instruction for each percpu variable
access. With hackbench, the performance improvement is 1.4% on Cortex-A9
(highbank). Taking an average of 30 runs of "hackbench -l 1000" yields:

Before: 6.2191
After: 6.1348

Will Deacon reported similar delta on v6 with 11MPCore.

The asm "memory clobber" are needed here to ensure the percpu offset
gets reloaded. Testing by Will found that this would not happen in
__schedule() which is a bit of a special case as preemption is disabled
but the execution can move cores.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>

Conflicts:
	arch/arm/kernel/smp.c
defconfigs: new governors
defconfigs: Update, switch to GZIP, add LZ4 Crypto
CPUFreq: Fix Makefile
Merge branch 'xb' of https://github.com/xboxfanj/kernel_msm into xb

Conflicts:
	arch/arm/configs/gee_defconfig