Merge pull request #21 from lalrae/i6400-mips64r6-PRIP4

This pull request contains the following features required for I6400 emulation:
* Config5.FRE feature allowing emulation of Status.FR=0 on a 64-bit FPU
  with Status.FR=1.
* Config5.LLB feature which makes LLbit visible to the software through
  CP0.LLAddr[0], it also adds ERETNC instruction.
* Enable 48-bit Physical Address on MIPS64.
* Bug fixes

Updates for #17

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips: add semihosting UHI support
test: LL/SC, LLB

Includes eretnc opcode workaround
test: 48 PA and improve XPA tests
test: UHI
test: FRE
AVP SUPPORT DO NOT UPSTREAM

AVP SUPPORT DO NOT UPSTREAM

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
SV SUPPORT DO NOT UPSTREAM

SV SUPPORT DO NOT UPSTREAM
AVP: 32->64 bit fixes
AVP: print PABITS
suppress warning