versatile_express: Move TC1 DTS file to the correct place

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
versatile_express: Add clocking and infrastructure components

... as required by Linux kernels 3.8+

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
fast_models: Add clocking and infrastructure components

... as required by Linux kernels 3.8+

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
fast_models: Update tree for RTSM A9x1

... missed in the previous commit.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
fast_models: Add Device tree for RTSM_VE-AEMV8a

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
fast_models: Fix RTSM's motherboard component compatible value

... as it is not the V2M-P1 hardware.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
fast-models: Add Cortex-R7x2 and Vexpress-R motherboard dts files

CC: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
verastile_express: Remove A9 PMU compatible values for non-A9 platforms

The ARM perf core code used to rely on the pmu node being
compatible with "arm,cortex-a9-pmu", even when the PMUs
of the different Cortex-A processors are not really
compatible... This is no longer required and actually
became harmful, so remove all the offending values
from Versatile Express DTS files.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
versatile_express: add Cortex-A57x1 SMM on V2M-1XV7 Device Tree

This patch adds a device tree source file for the V2S-A57x1 SMM, which
is an MP1 Cortex-A57 SMM implemented on a LogicTile Express 20MG
V2F-1XV7 board.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
versatile_express: Disable CA9 core tile sp804 timer

The motherboard sp804 timer is used, but core tile sp804 timer is not.
According to Russell King, the clock configuration is undocumented and
defaults to 32kHz which is not desireable. So mark core tile sp804 timer
as disabled.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
[PM: commit 34c2e5feeb0164baef76555141ad5b8dc84394bb in linux.git]
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
versatile_express: Add SCC to V2P-CA15_A7's device tree

SCC (Serial Configuration Controller) is used to set initial
conditions for the test chip (TC2). Its registers are also mapped
in normal address space and used to obtain runtime information
and for power management.

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
[PM: commit ceca0e1c3930c942cb849620ebe8fdafb55b5cda in linux.git]
versatile_express: Add CCI node to TC2 device-tree

The Versatile Express V2P-CA15_A7 (aka TC2) has a CCI-400 which is
needed to get Multi-Cluster Power Management (MCPM) working.

Signed-off-by: Jon Medhurst <tixy@linaro.org>
[PM: commit a2bdc32a527e817fdfa6c56eaa6c70f217da6c6c in linux.git]
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
versatile_express: Add 3.3V regulator missing in A7x1 SMM tree

Signed-off-by: Pawel Moll <pawel.moll@arm.com>
versatile_express: Add Cortex-A53x2 SMM on V2M-1XV7 Device Tree

This patch adds a device tree source file for the V2S-A53x2 SMM, which
is an MP2 Cortex-A53 SMM implemented on a LogicTile Express 20MG
V2F-1XV7 board.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
versatile_express: ca53x2: fix cpu node unit-address

Commit 4cf05447d0 ("versatile_express: Add Cortex-A53x2 SMM on V2M-1XV7
Device Tree") had a typo in the unit-address for one of the CPUs, which
can lead to dtc refusing to build the dtb unless forced to:

  dtc -I dts -O dtb -o vexpress-v2f-1xv7-ca53x2.dtb vexpress-v2f-1xv7-ca53x2.dts
  DTC: dts->dtb  on file "vexpress-v2f-1xv7-ca53x2.dts"
  ERROR (duplicate_node_names): Duplicate node name /cpus/cpu@0
  ERROR: Input tree has errors, aborting (use -f to force output)

This patch fixes up the unit-address for cpu@1 to correct this.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
versatile_express: ca53x2: add enable-method for cpu@1

Without an enable-method, the OS can't figure out how to boot the second
CPU. Add an enable-method ad additional information suitable for booting
the second CPU.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
fast-models: Correct the size of the GICC on Cortex A15 gics

GICv2 (Cortex A15/GIC 400) have CPU interface registers up to offset 0x1004
(the 32-bit GICC_DIR register a 0x1000). The GIC 400 documentation specifies
the CPU interface region as being 0x2000 in size.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
fast-models: Add virtualisation to aemv8

Add the GICH and GICV regions, as well as correcting the size of the GICC. Add
the maintenance interrupt.

Add the non-secure and virtual timers to the arch timer.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
fast_models: add virtio mmio device to RTSM Motherboard

Add the virtio MMIO device to the RTSM motherboard
include file.

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>