Define architecture dependent DSB/DMB/ISB macros
Don't define CP15 registers that aren't valid for the selected architecture
Define new inline TLB and cache functions.
Cleanup exception.S. Prepare for later unification of data_abort_handler() and prefetch_abort_handler().
First step in cleanup of locore.S. Fix initial stack allocation. Rename initial page table and use it for startup of secondary cores too. Same page table can be used for CPU hot plug and/or power management later.
Add new ARMv6 specific trap-v6.c.
Add new pmap code.
Fix handling of direct section unmapping.
    Use local variant of tlb_fush functions where appropriate
Merge r271716
Implement initial version of cpuinfo.
Rename pmap_tlb_flush_page. Use correct argument type  when calling tlb_flush functions. Minor cleanup nits.
Switch DMA coherent memory to normal uncacheable memory
Major cleanup of new pmap code.
Fix comments. Use macro for simplify pvh list Add first managed physical address.
Fix style.
Use new VM_PHYSSEG_SPARSE infrastructure
Use global tlb flush when servicing emulated access and modified bits.
Adjust NKPT2PG. Fix improper usage of ATTR_TO_L2. Add comments in pmap_init().
Remove now useless .arch directive form assembler files.
Don't read CP15 CBAR yet. This register is not present on all CPUs.