CHROMIUM: ARM: dts: nyan: Keep avdd 1.2 on.

This rail is needed by the audio codec to provide mic bias for the
mic-detect circuit which has to be active at all times.

BUG=none
TEST=With additional mic-detect changes, check that mic-detect works at
all times with rev1.

Change-Id: Icdabb4b2f2f7f721f31d7596c6960419ea30afe5
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177664
CHROMIUM: ASoC: tegra: Add mic detect to max98090 machine driver.

Adds mic detect to the tegra-max98090 driver.  This detects a headset
plugged in to the combo jack.  Forces the MICBIAS supply on so that the
mic detect will work even when not playing audio.

BUG=none
TEST=plug/unplug headset and see mic events with evtest.

Change-Id: I0441b10a6110ad8154829760f682c942838e91e5
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177665
CHROMIUM: ARM: dts: nyan: Add HP/Mic detect to nyan DT.

Configure the mic detect gpio and specify the headphone and mic detect
gpios for both rev0 and rev1 of nyan.

BUG=none
TEST=check mic and hp detect with evtest.

Change-Id: I251902143912ed9ad7184dbf6cafac5d71eb5596
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177666
CHROMIUM: tegra: initialize the reference counts for power domains

We have the reference counts for DISA/DISB/VENC/SOR power domains.
This patch initializes the reference counts to reflect the real power
status.

BUG=None
TEST=Build and boot tested

Change-Id: Id5315fc3c4e538f011896ace00b6751f7773e449
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/178020
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: ARM: dts: nyan: Fix regulator wrong regs

The reg properties of the regulators are off by one.

Based on work by: Mark Zhang

BUG=None
TEST=Booted kernel and verified regulators are initialized properly.

Change-Id: I46eb50c93b66741c7b35e3fdda8314ac3e6ebfde
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/178012
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
dma: tegra: fine granularity residual for tx_status

cras requires a bit more finer detail for residual reporting
for its low latency model.  This change has the dma driver
check the hardware for how many words have been transferred
in the current DMA  and takes it into account
when reporting residual.

BUG=chrome-os-partner:21344
TEST=cras_test_client and youtube sound improved

Change-Id: I6bcea1b38a7e623bf46717c32d68cb1ee97f8e4a
Signed-off-by: Christopher Freeman <cfreeman@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/177690
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Commit-Queue: Dylan Reid <dgreid@chromium.org>
Tested-by: Dylan Reid <dgreid@chromium.org>
clk: tegra: use pll_ref as the pll_e parent

Use pll_ref instead of pll_re_vco as the pll_e parent on Tegra114. Also
add a 12Mhz pll_ref table entry for pll_e for Tegra114. This prevents
the system from crashing at bootup because of an unsupported pll_re_vco
rate.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>

Patch posted upstream at:
    http://www.spinics.net/lists/linux-tegra/msg14516.html

BUG=none
TEST=boot the device

Change-Id: I9a4d96447e292db9764fe253055521fbdc154c95
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/178408
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: David James <davidjames@chromium.org>
UPSTREAM: regulator: as3722: set the correct current limit

Simple fix to set the correct current limit for SD0/1/6.

Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Fixes: bc407334e9a6 (regulator: as3722: add regulator driver for AMS AS3722)
Cc: stable@vger.kernel.org
(cherry picked from commit c3498f040d54b3deb6755af5144fe6cd50db8ddb)

BUG=None
TEST=Verified /sys/class/regulator/regulator.6/microamps for SD1 on Venice2

Change-Id: If32a80800f39948f25a4a4d5b2f7b6b3c31d3e2e
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/178474
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: David James <davidjames@chromium.org>
CHROMIUM: pinctrl: tegra: add suspend-resume support

Adding the PM function of Tegra pinctrl driver. And register them with
syscore so that pins are reconfigured before the devices relying on them
resume.

Based on the work by: Pritesh Raithatha <praithatha@nvidia.com>

BUG=none
TEST=test with LP0/LP1 suspend-resume

Change-Id: I62ec3876ac0605b5e59697929b539afc1c053848
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/176991
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: regulator: as3722: assign n_voltages by the low voltage mode

If the SD0's minimum voltage is 0.4V, the n_voltages should be 0x6E + 1,
and the voltage ranges from 0.41V to 1.5V.

BUG=None
TEST=Boot on Nyan Rev0 and Rev1

Change-Id: I6fc8ddda78b668c10d5268b4f4af183e1f7b84f6
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178490
CHROMIUM: mmc: tegra: add PM support

Adding PM function support for Tegra SDHCI driver.

BUG=none
TEST=test with LP0/LP1

Change-Id: Ie7df2b15a36fdb14441ea6e08f1d67f2aa065185
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/176992
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: gpio: tegra: moving suspend function to syscore

When supporting deep sleep mode on Tegra which means except always-on
power partitions and SDRAM in self-refresh mode, other blocks and main
power will be shut off. The GPIO settings can't be retained across power
cycle. It will cause the resume flow be broken when some of the early
resume functions or IRQ accessing the device that depends on GPIO to work
normally. Moving the suspend/resume function from system to syscore to
resolve this.

BUG=none
TEST=test with LP0/LP1 suspend-resume

Change-Id: I18b17d3da276565638f7793883000658b7a5e6cc
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/176993
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: i2c: tegra: moving suspend/resume function from system to noirq

The waking up of I2C device would keep the interrupt when it woke up the
system. And trigger the interrupt after system finish _noirq resume
services. Then it caused I2C access error due to the I2C host not
resumed yet. Moving it from system to noirq to solve this issue.

BUG=none
TEST=tested with LP1/LP0

Change-Id: I81e71f778582923f7f4f69b9303e4cc645cbf3c7
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/178500
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: ARM: tegra: save/restore reset handler for suspend

The reset handler was stored in IRAM. And it will be powered off by
vdd_core in the LP0. This patch provide functions for LP0 to
save/restore reset handler.

BUG=none
TEST=test with LP0/LP1

Change-Id: I54864ad01f15e6738bcba8078c6a8aaca86e7b90
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/176994
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: ARM: tegra: add suspend/resume for TSC

The clock source of the system counter (TSC) is not available when the
system suspends to deep sleep mode. It needs to be switched to the 32KHz
before suspending and restored after resuming.

BUG=none
TEST=test with LP0/LP1

Change-Id: Ic91da5d9c167b3f179e51cf1c2092e10ca5ebc38
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/176995
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: ARM: tegra: suspend/resume for debug UART

Adding suspend/resume support for debug UART.

BUG=none
TEST=test with LP0/LP1

Change-Id: Ic0e9511abe2f09c52204ba98a6ebd381c605a65f
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/176996
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: regulator: as3722: set enable time for SD0/1/6

Add enable time 600us for SD0/1/6 to ensure that we have
enough setup time for the power rail.

BUG=None
TEST=Can boot to console

Change-Id: Ib50094929971da69ce7fde46098f13aa608fee27
Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/178592
Reviewed-by: Dylan Reid <dgreid@chromium.org>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: ARM: tegra: clear the CPU init mask in deep sleep state

Adding the function to clear the CPU init mask when system prepares to
go into deep sleep state. The CPU init mask was used to determine the
power up sequence of secondary CPUs. When the system was resumed from
deep sleep state, it should fall back to cold boot flow not warm boot
flow.

BUG=none
TEST=test with LP0

Change-Id: If84776778705b99c19523c9f5b353b0ef663107e
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/176997
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
CHROMIUM: clk: Implement cbus and shared clocks

cbus clocks are virtual clocks which implement coordinated changes to
clock rates. These are needed because changing a PLLs rate cannot be
done with active child clocks. Therefore the child clocks are moved to
a backup pll during the PLL rate change.
shared clocks are virtual clocks which implement clock policies (eg min
or max rates).

BUG=None
TEST=None

Change-Id: I8bdf89790fb63fdefa10007e7a174053c56ae25f
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177719
CHROMIUM: clk: tegra: Implement common cbus/shared clocks

Tegra114 and Tegra124 share a set of cbus/shared clocks. Implement them
in a common file.

BUG=None
TEST=None

Change-Id: Ic599b6f85271488494d0bc5982c8d4f794517c1b
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/177730
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>