drm/vc4: Fix validation of store tile buffer general address.

The "don't clear some of the tile buffer" bits are in the low bits of
the address.

Signed-off-by: Eric Anholt <eric@anholt.net>
drm/vc4: Use real waits with measured timeouts.

Signed-off-by: Eric Anholt <eric@anholt.net>
drm/vc4: Drop a debug message from initial bringup.

Signed-off-by: Eric Anholt <eric@anholt.net>
drm/vc4: Allow stencil uniform setup.

Nothing in this register affects memory access, just how writes impact
the tile buffer.

Signed-off-by: Eric Anholt <eric@anholt.net>