clk: at91: fix PLL_MAX_COUNT macro definition

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
clk: at91: rework PLL rate calculation

The AT91 PLL rate configuration is done by configuring a multiplier/divider
pair.
The previous calculation was over-complicated (and apparently buggy).
Simplify the implementation and add some comments to explain what is done
here.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: Gael Portay <g.portay@overkiz.com>
clk: at91: rework rm9200 USB clock to propagate set_rate to the parent clk

The RM9200 USB clock is actually connected to a single parent (the PLLB)
on which we can apply a specific divider.
The USB clock divider does not allow for fine grained control on the USB
clock frequency, hence propagating the set_rate request to the parent is
the only choice we have to properly configure the USB clock rate.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: Gael Portay <g.portay@overkiz.com>
clk: at91: fix recalc_rate implementation of PLL driver

Use the cached values to calculate PLL rate instead of the register values.
This is required to prevent erroneous PLL rate return when the PLL rate
has been configured but the PLL is not prepared yet.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
clk: at91: fix div by zero in USB clock driver

Test rate value before calculating the div value to avoid div by zero.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: Gael Portay <g.portay@overkiz.com>