arm:sunxi:defconfig: Re-Enable symmetric multiprocessing for sun7i

Signed-off-by: Andreas Baierl<ichgeh@imkreisrum.de>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
arm:sunxi:defconfig: Enable CONFIG_FHANDLE required for systemd >= 209

Signed-off-by: Andreas Baierl<ichgeh@imkreisrum.de>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
sunxi: axp152: Keep DRAM / Vddr at bootloader set value

Some fex files contain wrong values, causing stability issues.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
sunxi: nand: Fix nand clk calculation

Before the u-boot dram cleanup u-boot would always set PLL5 factor m to
2 (reg value 1) and div p to 1, and get_cmu_clk in the nand code
would calculate the pll5p clk like this:

clk = 24 * factor_n * factor_k / div_p / factor_m;

aka:

clk = 24 * factor_n * factor_k / (div_p * factor_m);

This is wrong however, factor_m is not used to calculate pll5p, and div_p is
not a straight divider, but it divides by 2 ^ div_p. Since with the m == 2 and
p == 1 settings used before the dram cleanup, this happend to do the right
thing in the form of dividing by 2. But with the new dram code div_p is 0,
and then the old get_cmu_clk code fails with a divide by 0 error.

This commit fixes this, by changing the clk calculation to the correct form of:

clk = (24 * factor_n * factor_k) >> div_p;

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Merge remote-tracking branch 'upstream/stage/sunxi-3.4' into stage/sunxi-3.4_ve_mem.vsync
Reorganize deinterlacer routine