Updated readme, gitignore, some work on central_limit.py
central_limit.py done, writeup/schematic started

Generated plots from central_limit.py, reorganized files
Created circuit schematic using Fritzing
Started on writeup (lab1.tex)
Added new receiver schematics (.ckt, .png)
Added RLC filter text, plots to lab1.tex
Further text, figures for report
Additional writeup (results etc)
Finished lab report