[TASK] Add custom ip from altera used for soc designs
[TASK] Add subsystem for pcp and host for altera SoC
[TASK] renamed subsystem
[TASK] Add top system for soc system

- Note: Not incorporated the renaming of pcp subsystem
[TASK] Renamed subsystem name change
[TASK] Add openMAC and host Interface to design
[TASK] Removed DDR3 reset enable pin to push button to make work enable

- Download sof and press push button 1-2 times and run your application
[TASK] Test port added
[TASK] openMAC and Host Interface Interrupt connection added
[FIX] memory address range reduced to 27bit to solve known altera cr issue
[TASK] add missed h2f_reset_n pin
[TASK] Re-allignment the source code
[TASK] Clock reference modified
[TASK] Cleanup
[TASK] PLL updated for 13.1 tool chain
[TASK] Reconnected LED and DIP switches from Host
[TASK] Cleanup vhd files
[TASK] Add PHY config file for Altera SoC
[TASK] TX software and make file added
[TASK] Reset Sequence issue is fixed.
[TASK] Remove HPS from design

- Re work on mn_soc_pcp
- Disabled sysid from pcp

Note: Design is working from external memory