or1200-generic: verilator/tb: refactor parseArgs()

This reverts the change from if-else to if-continue introduced in
44ee3d8836b08918032b07963e14b6c94be6ceef, since the
latter just added more code and did not really make the code easier to
read.
It also changes the --or1k-elf-load argument to --elf-load,
to match the rest of the systems.
And finally it fixes a bug in the timeout argument.
or1200-generic: verilator/tb: add signal handler to catch ctrl-c

Without this, interrupting the simulation with ctrl-c will end
the simulation ungracefully, with the result that e.g. data
will be missing from VCD dumps etc.
or1200-generic: verilator/tb: let time be unsigned

Negative time values doesn't make sense, so let just handle
unsigned quantities.
or1200-generic: verilator/tb: track PC and print status on exit
or1200-generic: verilator/tb: add support to read binary program files
or1200-generic: verilator/tb: catch verilog $finish() statements

Without this, simulation isn't ended gracefully on verilog
$finish() statements.