net: ethernet: update dependency and help text of mvneta

With the introduction of the support for Armada 375 and Armada 38x,
the hidden Kconfig option MACH_ARMADA_370_XP is being renamed to
MACH_MVEBU_V7. Therefore, the dependency that was used for the mvneta
driver can no longer work. This commit replaces this dependency by a
dependency on PLAT_ORION, which is used similarly for the mv643xx_eth
driver.

In addition to this, it takes this opportunity to adjust the
description and help text to indicate that the driver can is also used
for Armada 38x. Note that Armada 375 cannot use this driver as it has
a completely different networking unit, which will require a separate
driver.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: David S. Miller <davem@davemloft.net>
of: Allows to use the PCI translator without the PCI core

Translating an address from a PCI node of the device-tree into a CPU
physical address doesn't require the core PCI support. Those
translations are just related to the device tree itself.

The use case to translate an address from a PCI node without actually
using the PCI core support is when one needs to access the PCI
controller without accessing any PCI devices.

Marvell SoCs, such as Kirkwood, Dove or Armada XP for instance, come
with an IP of a PCI controller. In the registers of this controller
are stored the ID and the revision of a SoC. With this patch it will
be possible to read the SoC ID of a board without any PCI device and
then without the PCI core support.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Allows to get the SoC ID even without PCI enabled

The address translation of a PCI node don't require anymore the PCI
support in the kernel. This translation is mandatory to be able to
read the SoC ID which is stored in the PCI controller of the mvebu
SoCs.

This patch selects the symbol needed to get only this translation for
all the mvebu platforms.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
i2c: mv64xxx: refactor message start to ensure proper initialization

Because the offload mechanism can fall back to a standard transfer,
having two seperate initialization states is unfortunate. Let's just
have one state which does things consistently. This fixes a bug where
some preparation was missing when the fallback happened. And it makes
the code much easier to follow. To implement this, we put the check
if offload is possible at the top of the offload setup function.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: stable@vger.kernel.org # v3.12+
Fixes: 930ab3d403ae (i2c: mv64xxx: Add I2C Transaction Generator support)
ARM: PJ4B: Add cpu_suspend/cpu_resume hooks for PJ4B

PJ4B needs extra instructions for suspend and resume, so instead of
using the armv7 version, this commit introduces specific versions for
PJ4B.

Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: remove the address parameter for ll_set_cpu_coherent

In order to be able to deal with the MMU enabled and the MMU disabled
cases, the base address of the coherency registers was passed to the
function. The address by itself was not interesting as it can't change
for a given SoC, the only thing we need is to have a distinction
between the physical or the virtual address.

This patch add a check of the MMU bit to choose the accurate address,
then the calling function doesn't have to pass this information.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: ll_set_cpu_coherent always uses the current CPU

ll_set_cpu_coherent is always used on the current CPU, so instead of
passing the CPU id as argument, ll_set_cpu_coherent() can find it by
itself.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
ARM: mvebu: Remove the unused argument of set_cpu_coherent()

set_cpu_coherent() took the SMP group ID as parameter. But this
parameter was never used, and the CPU always uses the SMP group 0. So
we can remove this parameter.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Split low level functions to manipulate HW coherency

Actually enabling coherency and adding a CPU on a SMP group are two
different operations which can be done separately. This patch splits
this in two functions.

Moreover as they use common pattern, this patch also creates local low
level functions (ll_get_coherency_base and ll_get_cpuid) to be used by
the exposed functions (ll_add_cpu_to_smp_group and
ll_enable_coherency)

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Low level function to disable HW coherency support

When going to deep idle we need to disable the SoC snooping (aka
hardware coherency support). Playing with the coherency fabric
requires to use assembly code to be sure that the compiler doesn't
reorder the instructions nor do wrong optimization.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Extend the pmsu registers

The initial binding for PMSU were wrong. It didn't take into account
all the registers from the PMSU and moreover it referred to registers
which are not part of PMSU.

The Power Management Unit Service block also controls the Coherency
Fabric subsystem. These registers are needed for the CPU idle
implementation for the Armada 370/XP, it allows to enter a deep CPU
idle state where the Coherency Fabric and the L2 cache are powered
down.

This commit add support for a new compatible for the PMSU node
including the block related to the coherency fabric. It also keeps
compatibility with the old binding

This patch also adds warnings if one of the base registers set can't
be ioremapped.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: dts: mvebu: Introduce a new compatible for the PMSU node

The initial binding for PMSU were wrong. It didn't take into account
all the registers from the PMSU and in the other hand refereed to
registers which are not part of PMSU. This commit introduces a new
compatible for the PMSU node and annotates the previous one as
obsolete. However we still continue to support it during a few
releases.

Cc: devicetree@vger.kernel.org
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Allow to power down L2 cache controller in idle mode

This commit adds a function which adjusts the PMSU configuration to
automatically power down the L2 and coherency fabric when we enter a
certain idle state.

This feature is part of the Power Management Service Unit of the
Armada 370 and Armada XP SoCs.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Add the PMSU related part of the cpu idle functions

The cpu idle support will need to access to Power Management Service
Unit. This commit adds the architecture related functions that will be
used in the idle path of the cpuidle driver.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Set the start address of a CPU in a separate function

Setting the start (or boot) address of a CPU is no more used only
during SMP bring up, but it will also be used by the CPU idle
functions or later by the CPU hot plug ones.

This commit moves it in a separate function.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: Register notifier callback for the cpuidle transition

In order to have well encapsulated code, we use notifier callbacks for
CPU_PM_ENTER and CPU_PM_EXIT inside the mvebu power management code.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoC

Add the wfi, cpu idle and cpu deep idle power states support for the
Armada XP SoCs.

All the latencies and the power consumption values used at the
"armada_370_xp_idle_driver" structure are preliminary and will be
modified in the future after running some measurements and analysis.

Based on the work of Nadav Haklai.

Signed-off-by: Nadav Haklai <nadavh@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
ARM: mvebu: register the cpuidle driver for the Armada XP SoCs

The cpuidle is a platform driver so we register the device just after
the initialization of the board in an arch_initcall.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>