ARM: 7755/1: handle user space mapped pages in flush_kernel_dcache_page

Commit f8b63c1 made flush_kernel_dcache_page a no-op assuming that
the pages it needs to handle are kernel mapped only.  However, for
example when doing direct I/O, pages with user space mappings may
occur.

Thus, continue to do lazy flushing if there are no user space
mappings.  Otherwise, flush the kernel cache lines directly.

Signed-off-by: Simon Baatz <gmbnomis@gmail.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: <stable@vger.kernel.org> # 3.2+
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7629/1: mm: Fix missing XN flag for for MT_MEMORY_SO

Commit 8fb54284ba6a {ARM: mm: Add strongly ordered descriptor support}
added XN flag at section level but missed it at PTE level.

Fix it by adding the L_PTE_XN to MT_MEMORY_SO PTE descriptor.

Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7928/1: kconfig: select HAVE_EFFICIENT_UNALIGNED_ACCESS for CPUv6+ && MMU

Modern ARM CPUs can perform efficient unaligned memory accesses in
hardware and this feature is relied up on by code such as the dcache
word-at-a-time name hashing.

This patch selects HAVE_EFFICIENT_UNALIGNED_ACCESS for these cores and
reworks the kconfig select logic for DCACHE_WORD_ACCESS to use the new
symbol.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

Revert "ARM: fix user unalignment prefetch abort"

This reverts commit 47e6bdeb9c62b707528ebce7bb1f0238289aaf67.

ARM: cacheflush: split user cache-flushing into interruptible chunks

Flushing a large, non-faulting VMA from userspace can potentially result
in a long time spent flushing the cache line-by-line without preemption
occurring (in the case of CONFIG_PREEMPT=n).

Whilst this doesn't affect the stability of the system, it can certainly
affect the responsiveness and CPU availability for other tasks.

This patch splits up the user cacheflush code so that it flushes in
chunks of a page. After each chunk has been flushed, we may reschedule
if appropriate and, before processing the next chunk, we allow any
pending signals to be handled before resuming from where we left off.

Signed-off-by: Will Deacon <will.deacon@arm.com>

ARM: cacheflush: don't bother rounding to nearest vma

do_cache_op finds the lowest VMA contained in the specified address
range and rounds the range to cover only the mapped addresses.

Since commit 4542b6a0fa6b ("ARM: 7365/1: drop unused parameter from
flush_cache_user_range") the VMA is not used for anything else in this
code and seeing as the low-level cache flushing routines return -EFAULT
if the address is not valid, there is no need for this range truncation.

This patch removes the VMA handling code from the cacheflushing syscall.

Signed-off-by: Will Deacon <will.deacon@arm.com>

ARM: 7917/1: cacheflush: correctly limit range of memory region being flushed

The __do_cache_op function operates with a 'chunk' size of one page
but fails to limit the size of the final chunk so as to not exceed
the specified memory region. Fix this.

Change-Id: Iebc8558947df1fcf8dc5b84123a7df877b67e161
Cc: <stable@vger.kernel.org>
Reported-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
msm: mdss: Move iommu attach after overlay start in pan display

IOMMU page faults can happen if iommu is attached in pan display
if continuous splash is enabled as splash fetches from physical
memory. Splash cleanup is performed in overlay start and hence
move iommu attach after splash cleanup is done.

Change-Id: I703c925f964527f33108a3a09ee1ffdc0a3003cd
Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org>
msm: mdss: use appropriate api to get length of scatterlist

Moving away from using sg_dma_len() api to be inline with
ion driver, use sg->length for scatterlist length.

Change-Id: I3a33340dc1bda5b24a406c29601aff4d5b2c5748
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
msm: mdss: add LP/HS mode DCS CMD support to MDP5 targets

LP/HS mode configuration for DCS Commands in currently not
supported on MDP5 targets. Add the required support to meet
all panel requirements.

Change-Id: Ib31ddc02f151033a59d6297c8f1a4f8897378947
Signed-off-by: Shuo Yan <shuoy@codeaurora.org>
msm: mdss: enable runtime autosuspend for mdp device

With MDSS idle power collapse feature enabled, it is possible that
the runtime suspend callback for MDP device to be called when there are
no display updates. This results in MDSS GDSC to be turned off in idle
screen usecases, and would subsequently be turned back on upon the next
update. However, toggling GDSC can be an expensive operation and should
only be done when it is expected to be off for a substantial time. To
achieve this, enable the runtime autosuspend status for the mdp device.

Change-Id: I6e4127efe7b01d7e164b0763d34995c82c2e8be9
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
mdss: mdp: reset init phase and phase step to default

reset the init phase and phase step registers to default
when the pixel extension are not calculated in userspace.

Change-Id: I876f1628fb46901a07deb1b97a4ab55f924612b0
Signed-off-by: Jeevan Shriram <jshriram@codeaurora.org>
Signed-off-by: Ujwal Patel <ujwalp@codeaurora.org>
msm: mdss: restore mdss register when clocks are turned on

When MDSS idle power collapse feature is enabled, MDSS GDSC can be
turned off for idle screen usecases. As a result, whenever MDSS
GDSC is turned back on, all MDSS registers need to be restored.
Current implementation restores this as part of bus bandwidth control
API which is only called whenever interface clocks are turned on.
However, the correct approach is to restore the hardware state whenever
any new register programming needs to be done. Therefore, move the
call to restore MDSS state from the bus bandwidth control function over
to the MDSS clock control function.

Change-Id: I85c934b8050b217253be98d9630ef922e76b6216
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
msm: mdss: Vote for bandwidth reference count for command transfer

Bandwidth vote needs to be enabled for DCS commands to be sent
during static screen on command mode panels.

Change-Id: I267c910dac9610b230f0138909c0dc8ca5797f11
Signed-off-by: Vishnuvardhan Prodduturi <vproddut@codeaurora.org>
msm: mdss: fix underrun between splash screen and boot animation

When continuous splash is enabled, avoid timing
engine flush in the first commit.

Change-Id: I11e7f86c910aa4dcaea3fcd72ec24cbbea450db2
Signed-off-by: Ingrid Gallardo <ingridg@codeaurora.org>
msm: mdss: support mdp idle power collapse only for cmd mode panels

With MDP idle power collapse feature enabled, MDSS GDSC gets turned off
whenever there are no updates sent to the panel which results in all
hardware registers getting reset. These hardware registers need to be
restored whenever on the next udpate. Currently, this restore
functionality is only supported for command mode panels. However it is
possible that there could be additional framebuffer devices that may be
active (such as a writeback device) in conjunction with the primary
panel. In such cases, if idle power collapse happens, then these control
paths may not get correctly restored leading to unexpected behaviors.
Fix this by preventing MDP idle power-collapse when such panels are
active.

Change-Id: I226e72086bb6232ae452a999d961c80f2841f833
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
msm8974: Enable ULPS mode for JDI panel

 * For real this time!

Change-Id: Ibd0a40f41ebd4419635c69c6378e4c330dad8424