hdl/modules/*/wb_acq_core/acq_cnt.vhd: fix late shots_cnt_all assert

Previously, the shots_cnt_all signal was only asserted one cycle
later than the pck_cnt_all. On cases where both signals go high
(last packet from the transaction) this is incorrect behavior
and causes other signals to misbehave.
hdl/modules/*/wb_acq_core/*: start reading before *_rdy signal

This behavior is necessary, as the UI interface signals states
that we must keep the enable signal high until the ready signal is
asserted. This behovior is also used by some arbitors to grant access
to the interface with the enable signal high.
hdl/modules/*/wb_acq_core/acq_ddr3_iface.vhd: remove *_gnt signals

We don't need to stall our interfaces when while we were not
granted access to the DDR3 controller. If we are not granted
access the *_rdy signals will already be low and stall our
interfaces.
hdl/testbench/*/**/full_tb/wb_acq_core_tb.v: emulate gnt signal behavior

In our design the UI interface *_rdy signals are only muxed to the
DDR3 controller when the PCIe core had granted access to it. Otherwise,
it keeps the signals low.