qseecom: Add support for bus scaling

Add support for scaling bus to various level:
LOW, MEDIUM, HIGH.  Expose IOCTL to user space
clients to enable selecting a specific bus bandwidth
setting.

Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
ASoC: msm: Add support for AAC decode in ADTS format

- Set AAC format based on the format value set in
  compress params
- Default is RAW AAC

Change-Id: I4815fdfa0bc0716a44cde0c4440eaa15180c03fc
Signed-off-by: ApurupaPattapu <apurupa@codeaurora.org>
msm: thermal: Update thermal sysfs nodes permission

Update the permissions of the sysfs nodes exposed
by the kernel thermal monitor.

Change-Id: Ib211852e8af74d17fd5e40585af2f03aa3ae7920
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
Revert "ARM: dts: msm: change emmc clock line drive strength"

This reverts commit 1da6b37497a7a80323994be13eacb0d439e47154.
This change caused regression that was fixed by commit
644bc429bce7e109475701a5f49477b97a8811ae "ARM: dts: msm: Reduce drive
strength on SDC1 clk for MSM8974Pro AB MTP" which reduced the drive
strength to 10mA addressing data corruptions. This commit was introduced
to address potential CRC issues that could rise due to the low drive
strength. This isssue will be revisted if there are any CRC errors
reported later on.
Update copyright year.

CRs-Fixed: 600184
Change-Id: I767f9fade577e2b7865bc3d78adf830f14bdb77a
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
msm: Fix RDI1 interface for VFE32

The RDI registers are not defined properly
for VFE32. Fixing this issue by making the
register addresses properly.

Change-Id: I19fb50a53ae239b5fc306684b5bb6c6f65c61382
Signed-off-by: Abhishek Kondaveeti <akondave@codeaurora.org>
msm: mdss: Correct element name for dtsi parsing

Color order was mistakenly updated without the qcom,
prefix, so the dtsi entry will have no effect.
Change updates the parse function so field will
be parsed correctly.

Change-Id: I69030f3a267572cc90bd33a53162deae34a4f168
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
msm: vidc: eliminate race condition in dynamic buffer mode

Function get_same_fd_buffer returned a pointer to
registered buffer, which shared the same fd as the
current buffer being mapped. While this buffer was
being accessed in map_and_register_buf(), it was
not guarded by the inst lock. So if the buffer was
erroneously freed, while it's still being accessed
in map_and_register_buf(), we may see a kernel
panic due to garbage values. To avoid this race
condition, introduce more checks in get_same_fd_buffer()
and return only the required handle information back to
map_and_register_buf.

Change-Id: I798c33dc344977c5db3bd74e5f863ca5cda14cb9
Signed-off-by: Arun Menon <avmenon@codeaurora.org>
msm: audio: qdsp6v2: disable read interrupts for smd channels

SMD channels are configured to send interrupts when the remote end
reads from the channels. Disable this behavior to reduce number
of interrupts.

Change-Id: I4c4f76c038b5f9b79c164a53306ccbe31c415d74
Signed-off-by: Haynes Mathew George <hgeorge@codeaurora.org>
ARM: dts: msm: enable LP11 configuration for ssd2080m

ssd2080m requires panel reset after LP11 timing starts,
add extra 50ms delay after reset to ensure the safety.

Change-Id: I5278443a5555dcc59498a52984c9523134b35d50
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
crypto: msm: Handle error case

Release memory and disable clk when sps_init fails.

Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
crypto: msm: Add support for setting XTS data unit size

Based on the context flags set by client, set XTS_DU_SIZE
register to sector size of 1KB, or the actual total length
of the packet.

Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
ARM: dts: msm: bus scaling for crypto operation

Add documentation for optional flag "support-bus-scaling". This
flag indicates if platform supports bus scaling request for
crypto operation.

Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
crypto: msm: optimize ce bandwith scaling

Encryption processing at qcrypto driver includes three main steps:
set ce high bandwidth and enable ce clock in cra_init, then send
encrytion request, and at last set ce low bandwidth and disable
clock in cra_exit. This process is fine for the use case where
there are lots of requests between cra_init and cra_exit, but will
introduce large overhead for mmc layer disk encryption as it calls
cra_init, queue request and cra_exit for every encryption request.

It is not necessary to set low bandwidth and disable clock for every
encrypt request when it is completed. So we delay these scaling down
tasks for a while, and just scale down the last request when timer
expires so as to amortize and decrease the overhead.

Signed-off-by: Zhen Kong <zkong@codeaurora.org>
crypto: msm: fix issues in ce clock disable processing

In the situation of more than one requests, the ce clock may get
errorneously disabled even when there are active requests. The
scaling operation is then modified to fix the problem and ensure
all requests are completed when disable the clock. We also clean
up the related codes.

Signed-off-by: Zhen Kong <zkong@codeaurora.org>
crypto: msm: multiple qcrypto support

This patch provides support for multiple qcrypto devices
with the qcrypto driver.

Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
crypto: msm: qce50 ota crypto support

Kasumi/snow-3g f8/f9 are defined by 3gpp, as the algorithms for
UMTS, and LTE for over the air ciphering and integrity. The
algorithms are supported by crypto 5 hardware. This patch
enables qce50 driver to provide Kasumi/snow-3g f8/f9
ciphering and integrity services.

Acked-by: hemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
crypto: msm: fix hmac hashing issues with various key size

hmac-sha1 and hamc-sha256 have variable mac key up to a block size.
If user provides a key that is less than the block size, the
key should be padded with zero to the block size before it is
given to the hw.

This padding was not done properly in the driver.
When switch engine between ahash hmac(sha1), hmac(sha256),
and ipsec, problem may happen. ipsec takes 20 bytes of key.
The generated digested data is wrong, even though everything looks
fine from driver. ipsec may fail.

Furthermore, this patch cleanup the driver to do proper setup of
hardware to use hw key or pipe key.

Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
crypto: msm: fix hmac ahashing issues with simultaneous multiple requests.

 This patch fixes two issues. One issue is to do with simultaneous requests
 of a ahash tfm. The other issue is to do with ahash import, and export
 functions.

 Agent issues chain of requests in sequence of init, followed
 by multiple updates, and final to the crypto driver for the hashing of a
 buffer. Each request can be asynchrounous. After a request is complete,
 the next one in the sequence is issued.

 Multiple simultaneous async requests can be issued to the driver
 for the same tfm if they are for independent hashing.

 In the driver, the state variables such as trailing buffer, first
 block, last block are maintained in the driver. The
 state variables are maintained in the request context, instead of
 tfm context. Otherwise, simultaneous async requests can
 confuse each other. This patch moves those variables out of
 tfm context to request context to fix this issue.

 Agent above the driver can import/export ahash state of a request. This
 patch fixes a few issues in the driver to support import/export.
 First issue, the byte count returned from hw for hmac has 64 bytes of
 padding on the first request to the hardware. In the import/export this
 special case needs to be accomodated.

 The 2nd issue is the state buffer is only updated after hardware operation
 complete. For the first, data being accumulated in the trailing buffer,
 and if request has not ever issued to the hw, when import function comes,
 the trailing data needs to be exported. This patch uses trailing
 buffer directly as state buffer variable for import and export.
 The context update functions after hareware request complete are not
 necessary and they are removed. The last issue is to do with state
 variable count. It was not initialized. That may cause hashing generated
 wrong  digest after export and import.

Acked-by: Chemin Hsieh <cheminh@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: Zhen Kong <zkong@codeaurora.org>
crypto: msm: add pm wakeup support for qcrypto driver

Add support for holding system from suspending while an operation
is in progress (when clks are enabled).  This is done by invoking
pm_stay_awake before enabling clks (when a crypto operation is
initiated) and invoking pm_relax when crypto operation is done.

Signed-off-by: Zhen Kong <zkong@codeaurora.org>
crypto: msm: Fix key length setting

Hardcoding key length to a constant value results in overwriting
command element information in the command descriptor beyond what
is allocate for the key information in the command element list.
This results in corruption of the command list in the case where
command descriptors are used for configuring crypto registers and
needlessly writing to key registers that are not relevant to the
operation (when writing to registers directly), and thus leads to
crypto operation failures. Fix is to use the key length based on
what is requested by the client.

Signed-off-by: Zhen Kong <zkong@codeaurora.org>