MIPS64: Update sim fp code to use FR=1 mode, which is default for mips64.
MIPS64: Use real ldc1/sdc1 to load/store doubles.

With FR=1 mode (32 64-bit FP regs), we can no longer use paired
lwc1/swc1 to load/store doubles, since we are not using reg pairs:
like f0, f1.
MIPS64: Implement mthc1/mfhc1 and dmtc1/dmfc1 instructions.

In assembler and simulator (already in disasm).

Also fix a couple sim bugs in FP instruction implementation.
MIPS64: Fix all the FP cctests to work in fr1 mode.

Also need a change to macro-asm, for some called functions.