i965: Create a helper function for emitting PIPE_CONTROL flushes.

These days, we need to emit PIPE_CONTROL flushes all over the place.
Being able to do that via a single function call seems convenient.

Broadwell will also increase the length of these packets by 1; with the
refactoring, we should have to do this in substantially fewer places.

v2: Add back forgotten intel_emit_post_sync_nonzero_flush (caught by
    Eric Anholt).  Drop unlikely() from BLT_RING check.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Emit full-length PIPE_CONTROLs for (non-write) flushes.

The PIPE_CONTROL packet actually has 5 DWords on Gen6+:
1. Header
2. Flags
3. Address
4. Immediate Data: Lower DWord
5. Immediate Data: Upper DWord

We just never emitted the last one.  While it appears to work, it's
probably safer to emit the entire thing.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Use full-length PIPE_CONTROL packets for workaround writes.

I believe that PIPE_CONTROL uses the length field to decide whether to
do 32-bit or 64-bit writes.  A length of 4 would do a 32-bit write,
while a length of 5 would do a 64-bit write.  (I haven't verified this,
though.)

For workaround writes, we don't care what value gets written, or how
much data.  We're only writing something because hardware bugs mandate
that do so.  So using a 64-bit write should be fine.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Create a helper function for emitting PIPE_CONTROL writes.

There are a lot of places that use PIPE_CONTROL to write a value to a
buffer (either an immediate write, TIMESTAMP, or PS_DEPTH_COUNT).
Creating a single function to do this seems convenient.

As part of this refactor, we now set the PPGTT/GTT selection bit
correctly on Gen7+.  Previously, we set bit 2 of DW2 on all platforms.
This is correct for Sandybridge, but actually part of the address on
Ivybridge and later!

Broadwell will also increase the length of these packets by 1; with the
refactoring, we should have to adjust that in substantially fewer
places, giving us confidence that we've hit them all.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Re-combine the Gen4-5 and Gen6+ write_depth_count functions.

Now that we have a helper function that handles the PIPE_CONTROL
variations between the various platforms, these are basically the same.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
!UPSTREAM i965: Introduce an OUT_RELOC64 macro.

Broadwell uses 48-bit addresses.  The first DWord is the low 32 bits,
and the second DWord is the high 16 bits.

This patch is broken and superceded by others on the mailing list

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Update PIPE_CONTROL packet lengths for Broadwell.

On Broadwell, PIPE_CONTROL needs an extra DWord to accomodate the
48-bit addressing.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Fix MI_STORE_REGISTER_MEM for Broadwell.

It now takes a 48-bit address.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
i965: add struct and SFID for pixel interpolator messages

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Add #defines for new Broadwell math functions.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Add SFID #defines for media stuff.

While we probably won't ever use these, having them makes it easy to
share disassembler code between intel-gpu-tools and Mesa.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
i965: Add a new representation for Broadwell shader instructions.

Broadwell significantly changes the EU instruction encoding.  Many of
the fields got moved to different bit positions; some even got split
in two.

With so many changes, it was infeasible to continue using struct
brw_instruction.  We needed a new representation.

This new approach is a bit different: rather than a struct, I created a
class that has four DWords, and helper functions that read/write various
bits.  This has several advantages:

1. We can create several different names for the same bits.  For
   example, conditional modifiers, SFID for SEND instructions, and the
   MATH instruction's function opcode are all stored in bits 27:24.

   In each situation, we can use the appropriate setter function:
   set_sfid(), set_math_function(), or set_cond_modifier().  This
   is much easier to follow.

2. Since the fields are expressed using the original 128-bit numbers,
   the code to create the getter/setter functions follows the table in
   the documentation very closely.

To aid in debugging, I've enabled -fkeep-inline-functions when building
gen8_instruction.c.  Otherwise, these functions cannot be called by
gdb, making it insanely difficult to print out anything.

Kenneth Graunke wrote most of this code.  Damien Lespiau ported it to
C99.  Xiang Haihao added media fields.  Zhao Yakui added indirect
addressing support.  Eric Anholt added an assertion to make sure that
values fit in the alloted number of bits.

v2: Update for brw_reg_type_to_hw_type(), which necessitates passing
    brw_context pointers around everywhere.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com> [v2]
i965: Implement a disassembler for Broadwell's new instruction encoding

Heavily based on Keith Packard's existing brw_disasm.c code.  I've tried
to go through most of the pieces (like SFIDs) and update the lists to
include features added in recent generations.

v2: Port to use the C-based instruction emitters.  This allows us to use
    C99 array initializers, which tidies up some of the code.

v3: Improve decoding of render target write messages.

v4: Update for BRW_REGISTER_TYPE becoming an abstraction.

v5: Rebase on Chris Forbes' SFID message defines.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Matt Turner <mattst88@gmail.com> [v5]
i965: Add a new infrastructure for generating Broadwell shader assembly.

This replaces the brw_eu_emit.c layer for Broadwell.  It will be
used by both the vector and scalar shader backends.

v2: Port to use the C-based instruction representation.

v3: Fix destination register type for CMP.

v4: Pass brw to gen8_instruction functions (required by rebase).

v5: Remove bogus assertion on math instructions (caught by Piglit).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Matt Turner <mattst88@gmail.com> [v5]
i965: Create a new vec4 backend for Broadwell.

This replaces the old vec4_generator backend.

v2: Port to use the C-based instruction representation.  Also, remove
    Geometry Shader offset hacks - the visitor will handle those instead
    of this code.

v3: Texturing fixes (including adding textureGather support).

v4: Pass brw_context to gen8_instruction functions as required.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Create a new fragment shader backend for Broadwell.

This replaces the old fs_generator backend.

v2: Port to the C-based representation of assembly instructions.
    Fix texturing after the texture-grf merge.

v3: Add high quality derivative support.  Fix SET_SIMD4X2_OFFSET.

v4: Pass brw_context to gen8_instruction functions as required.

v5: Fixes for MRT, as well as zero render targets (alpha test only).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Reserve space for "Vertex Count" in GS outputs.

v2: Also increment ir->offset in the GS visitor, rather than at the
    final assembly generation stage (requested by Paul).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Duplicate gen7_atoms to gen8_atoms.

It's going to diverge significantly.  Starting out with a copy allows
future patches to change atoms one by one.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
i965: Use the Sandybridge VUE format on Broadwell as well.

It hasn't changed.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
i965: Bump generation assertions on workaround flushes.

These workaround flushes may not be necessary on Gen8.  Investigation is
needed.  Tentatively, let's do them out of caution.

v2: [chadv]
  - Comment that flush may not be needed.
  - Make assertion conditions symmetrical.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>