scu: fix incorrect clock domain on PCIe irq slave
eca: include new ECA, leave IRQs dangling on non-SCU tops

... had to fix broken vetar Manifest.py as well.
scu: use ActionQueue to ship actions to PCIe
build: stop hdlmake from even thinking of invoking git
vetar: invoke autogen.tcl
build: allow EXTRA_FLAGS to add compile options
initial commit of tmr_scu_bus
Added LM32 package with periphery and sw essentials
updated test program for scu irqs
wb_irq_scu_bus: changed dst addresses
scu_addac: added timer irq in top file
updated pointer to wrpc-sw
Merge branch 'proposed_master' into stefan-wip

Conflicts:
	ip_cores/etherbone-core
	ip_cores/general-cores
	ip_cores/wr-cores
	ip_cores/wrpc-sw
	syn/gsi_scu/control/scu_control.qsf
	top/gsi_scu/control/scu_control.vhd
fix submodule repositories
inital commit of wb_arria_reset
Merge branch 'proposed_master' of github.com:stefanrauch/bel_projects into proposed_master
ftm: include missing component definition and fix build
dac+mil: remove vhdl 2008 dependancy
mil: fix type errors (did anyone even compile this before commit???)
scu: remove stp file (should never have been pushed into git!)