* add a missing extra m-reg check for some LD/ST vector cases 
 
* implement 
  LD1/ST1 (multiple 1-elem structs to/from 2 regs 
  LD1/ST1 (multiple 1-elem structs to/from 3 regs 
  LD1/ST1 (multiple 1-elem structs to/from 4 regs  
  LD1R (single structure, replicate)  
  LD2R (single structure, replicate) 
  LD3R (single structure, replicate) 
  LD4R (single structure, replicate) 
  LD1/ST1 (single structure, to/from one lane) 
  LD2/ST2 (single structure, to/from one lane) 
  LD3/ST3 (single structure, to/from one lane) 
  LD4/ST4 (single structure, to/from one lane) 

I believe this completes the implementation of load and store
instructions for AArch64 ARMv8.



git-svn-id: svn://svn.valgrind.org/vex@2979 8f6e269a-dfd6-0310-a8e1-e2731360e62c