[Hexagon] Adding and64, or64, and xor64 instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222846 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16

Differential Revision: http://reviews.llvm.org/D6405


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222847 91177308-0d34-0410-b5e6-96231b3b80d8