Start pulling out memory signals.
Fix in/out mismatch.
Wire RAM signals through.
Fix for memories in BRAM.
Some FIFO fixes.
Add RAM modules for FIFOs.
Fix FIFOs with external memory.
Take functions into account for kernel memory.
Fix deadlock when there are multiple inputs to simulation.
Merge branch 'memory' of github.com:joewing/ScalaPipe into memory
Clean up HDL interconnect generation.
Instantiate the memory subsystem.
Fix for synthesis.
Fix some port connections.
Don't create memory ports if memory isn't used
Don't assign re/we if they don't exist.
Some memory signal fixes.
Change the default DRAM data width.
Fix FIFOs when used with memories with variable latency.
Start support for the Saturn board.