PSCI SMC handler improvements

The SMC handler for PSCI was not correctly handling calls from
secure states, or from AArch32.

This patch completes the handler implementation to correctly
detect secure callers and to clear the top bits in parameters from
AArch32 callers.

The patch also reorganises the switch statement to separate SMC64 and
SMC32 function IDs which allows the compiler to generate much smaller
code for the function.

Change-Id: I36b1ac81fb14253d257255d0477771d54fab0d11
Per-cpu data cache restructuring

This patch prepares the per-cpu pointer cache for wider use by:
* renaming the structure to cpu_data and placing in new header
* providing accessors for this CPU, or other CPUs
* splitting the initialization of the TPIDR pointer from the
  initialization of the cpu_data content
* moving the crash stack initialization to a crash stack function
* setting the TPIDR pointer very early during boot

Change-Id: Icef9004ff88f8eb241d48c14be3158087d7e49a3
Move CPU context pointers into cpu_data

Moving the context pointers for each CPU into the per-cpu data
allows for much more efficient access to the contexts for the
current CPU.

Change-Id: Id784e210d63cbdcddb44ac1591617ce668dbc29f
Remove early_exceptions from BL3-1

The crash reporting support and early initialisation of the
cpu_data allow the runtime_exception vectors to be used from
the start in BL3-1, removing the need for the additional
early_exception vectors and 2KB of code from BL3-1.

Change-Id: I5f8997dabbaafd8935a7455910b7db174a25d871
Remove broken assertion in console_putc()

The assertion in console_putc() would trigger a recursion that
exhausts the stack and eventually aborts.

This patch replaces the assertion with an error return if the
console has not been initialized yet.

Fixes ARM-software/tf-issues#208

Change-Id: I95f736ff215d69655eb5ba7ceac70dc1409d986a
Remove NSRAM from FVP memory map

This memory is not used by the FVP port and requires an additional
4KB translation table.

This patch removes the entry from the memory map and reduces the
number of allocated translation tables.

Fixes ARM-software/tf-issues#196

Change-Id: I5b959e4fe92f5f892ed127c40dbe6c85eed3ed72
Merge pull request #142 from athoelke/at/fix-console_putc

Remove broken assertion in console_putc()
Merge pull request #136 from athoelke/at/cpu-data

Per-cpu data cache restructuring
Merge pull request #137 from athoelke/at/no-early-exceptions

Remove early_exceptions from BL3-1
Merge pull request #138 from athoelke/at/cpu-context

Move CPU context pointers into cpu_data
Compile with '-Wmissing-include-dirs' flag

Add the '-Wmissing-include-dirs' flag to the CFLAGS and ASFLAGS
to make the build fail if the compiler or the assembler is given
a nonexistant directory in the list of directories to be searched
for header files.

Also remove 'include/bl1' and 'include/bl2' directories from the
search path for header files as they don't exist anymore.

Change-Id: I2475b78ba8b7b448b9d0afaa9ad975257f638b89
Merge pull request #140 from athoelke/at/psci_smc_handler

PSCI SMC handler improvements
Merge pull request #143 from athoelke/at/remove-nsram

Remove NSRAM from FVP memory map
Initialise CPU contexts from entry_point_info

Consolidate all BL3-1 CPU context initialization for cold boot, PSCI
and SPDs into two functions:
*  The first uses entry_point_info to initialize the relevant
   cpu_context for first entry into a lower exception level on a CPU
*  The second populates the EL1 and EL2 system registers as needed
   from the cpu_context to ensure correct entry into the lower EL

This patch alters the way that BL3-1 determines which exception level
is used when first entering EL1 or EL2 during cold boot - this is now
fully determined by the SPSR value in the entry_point_info for BL3-3,
as set up by the platform code in BL2 (or otherwise provided to BL3-1).

In the situation that EL1 (or svc mode) is selected for a processor
that supports EL2, the context management code will now configure all
essential EL2 register state to ensure correct execution of EL1. This
allows the platform code to run non-secure EL1 payloads directly
without requiring a small EL2 stub or OS loader.

Change-Id: If9fbb2417e82d2226e47568203d5a369f39d3b0f
Eliminate psci_suspend_context array

psci_suspend_context is an array of cache-line aligned structures
containing the single power_state integer per cpu. This array is
the only structure indexed by the aff_map_node.data integer.

This patch saves 2KB of BL3-1 memory by placing the CPU
power_state value directly in the aff_map_node structure. As a
result, this value is now never cached and the cache clean when
writing the value is no longer required.

Fixes ARM-software/tf-issues#195

Change-Id: Ib4c70c8f79eed295ea541e7827977a588a19ef9b
Correctly dimension the PSCI aff_map_node array

The array of affinity nodes is currently allocated for 32 entries
with the PSCI_NUM_AFFS value defined in psci.h. This is not enough
for large systems, and will substantially over allocate the array
for small systems.

This patch introduces an optional platform definition
PLATFORM_NUM_AFFS to platform_def.h. If defined this value is
used for PSCI_NUM_AFFS, otherwise a value of two times the number
of CPU cores is used.

The FVP port defines PLATFORM_NUM_AFFS to be 10 which saves
nearly 1.5KB of memory.

Fixes ARM-software/tf-issues#192

Change-Id: I68e30ac950de88cfbd02982ba882a18fb69c1445
Merge pull request #144 from athoelke/at/init-context-v2

Initialise CPU contexts from entry_point_info (v2)
Merge pull request #145 from athoelke/at/psci-memory-optimization-v2

PSCI memory optimizations (v2)
Remove calling CPU mpidr from bakery lock API

The bakery lock code currently expects the calling code to pass
the MPIDR_EL1 of the current CPU.

This is not always done correctly. Also the change to provide
inline access to system registers makes it more efficient for the
bakery lock code to obtain the MPIDR_EL1 directly.

This change removes the mpidr parameter from the bakery lock
interface, and results in a code reduction of 160 bytes for the
ARM FVP port.

Fixes ARM-software/tf-issues#213

Change-Id: I7ec7bd117bcc9794a0d948990fcf3336a367d543
fvp: Fix register name in 'plat_print_gic_regs' macro

The 'plat_print_gic_regs' macro was accessing the GICC_CTLR register
using the GICD_CTLR offset. This still generates the right code in
the end because GICD_CTLR == GICC_CTLR but this patch fixes it for
the logic of the code.

Change-Id: I7b17af50e587f07bec0e4c933e346088470c96f3