axi_dmac: Add support for zero latency transfer switching

Right now there is always a period of one clock cycle where we can not transfer
any data when switching between two transfers. This patch modifies the data
mover to allow for zero latency. This fixes problems on the FMCOMMS1 platform

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
axi_dmac: address_generator: Fix disable race condition

If the address generator is disabled the very same cycle as it tries to put a
new address on the bus, it will keep sending this address forever and the core
will lock up

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>