ASoC: msm: audio-effects: improve logging

Make logs more meaningful by logging values where ever
applicable.

Change-Id: I0fd0e62e543480762096d64c7ee7c92eb1204126
Signed-off-by: Dhananjay Kumar <dhakumar@codeaurora.org>
ASoC: msm: qdsp6v2: Fix bit alignment in snd_codec params

Pointer member variables in snd_codec params break bit alignment and
causes data corruption. By changing these pointers to fixed size
array variables, the bit alignment is rectified. The size has been
set to max possible size. Also, remove params which are not required
anymore.

Change-Id: Ib87bbeb07b0df1ce8a81166b319976fe54c0f013
Signed-off-by: Amit Shekhar <ashekhar@codeaurora.org>
ASoC: msm: qdsp6v2: Add the matrix mixer call during ASM loopback

Add support for matrix mixer command. The render window start and
end are set up before RUN CMD for ASM loopback is issued. This
will ensure that audio data is not dropped and audio quality
is good.

CRs-fixed: 667925
Change-Id: I406d86e9805d9f57613c0349f11cfc729ef7a24c
Signed-off-by: Damir Didjusto <damird@codeaurora.org>
ASoC: msm: qdsp6v2: Cleanup of audio drivers

Using the format strings will remove need for typecasting.
This change cleans up audio msm drivers to use the kernel
defined data types and format specifiers for printk.

Change-Id: Ie1b3d5c8dcf868aa1cc7407d3e679976dffafc76
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
ASoC: msm: qdsp6v2: Cleanup of compress offload drivers

Clean up the format specifiers for compress offload drivers
and add compat ioctl support

Change-Id: I0829830336ec62c66658d6a5199d73b61249f791
Signed-off-by: Damir Didjusto <damird@codeaurora.org>
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
ASoC: qdsp6v2: update perf mode flag for LL capture cases

Read perf mode flag from platform data and update to the
audio client structure, so that the right settings can be
applied to ADM for Low-latency capture use-case.
Also, update the correct bit value for ASM perf mode flag
sent to DSP.

Change-Id: If1f8b9e657a409fd9d2af19ff004a797fd987788
Signed-off-by: Banajit Goswami <bgoswami@codeaurora.org>
ASoC: msm: q6dspv2: add pause/resume support for audio record

Add support for pause/resume functionality for audio capture
path. When application calls stop()for for pausing, suspend
the ASM stream, so that hardware resources can be released.
Again when resuming capture streams with prepare()->start(),
ASM open and the routing call should not be called again.

CRs-fixed: 692084
Change-Id: I59e014696ab0a8c473b87361ac9b739adf538d32
Signed-off-by: Banajit Goswami <bgoswami@codeaurora.org>
ASoC: wcd9320: Fix micbias setting for MAD

For Microphone Activity Detection (MAD) to work properly, it is required
to update the micbias setting correctly to indicate the micbias is
external or internal. Correct the MAD micbias settings to account for
type of micbias (internal or external).

CRs-fixed: 684818
Change-Id: If209f9e4ad971a25fd28848ba7ba297c4f3dbf06
Signed-off-by: Bhalchandra Gajare <gajare@codeaurora.org>
ASoC: msm: qdsp6v2: Change client names for ion alloc

ASM and AFE are using the same client name when requesting
ion alloc. This is making it harder to debug which client
requested the memory.  Changing the client names to more
descriptive names.

CRs-fixed: 714707
Change-Id: Id774ce06ff5300da1de5b653812a02a22a47147c
Signed-off-by: Damir Didjusto <damird@codeaurora.org>
ASoC: msm: qdsp6v2: update int to size_t

Int aren't same size as size_t in 64bit kernel. This actually cause part of
the stack to be overwritten

Change-Id: I0ebff1fb9030fdb93a6889ee02329599ae2800fb
Signed-off-by: Fred Oh <fred@codeaurora.org>
arm/dts: Scope pic16F setup for Oppo board properly

 * OP doesn't have this hardware, and it's causing and interrupt storm
   on the i2c bus. Scope it to the devices which actually have it.

Change-Id: Ic28f73026c8ded44bf6ae84a939c26e4379e4b87
msm: kgsl: Fix gpu idle check

Fix the mask being used to check whether gpu has a pending
irq or not and check whether gpu status is idle before checking
for a pending irq. If pending irq is checked before the gpu
status then there is a possibility of the irq being set after
it has been checked but before the gpu status is checked which
will result in the logic detecting that gpu is idle with a
pending irq.

Change-Id: I5f97b6f3f4c6b58c95e91604ae87330d06685962
CRs-Fixed: 647176
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>

msm: kgsl: Change check for gpu idle

Check whether gpu is idle by checking if any of its bits in
RBBM_STATUS is set except for AHB and HI bits.

Change-Id: I3dac8131a637c046d4c5cfde5935483cefaf8b53
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>

msm: kgsl: Clean-up unneeded power code

No platforms with direct ebi1 connections exist, nor
is idling before changing the frequency needed.

Change-Id: I80911c81ef7303e229494ce6ba3df57ee25b24a5
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>

msm: kgsl: Set the GX rail voltage before enabling it

Make sure the rail turns on with a consistent voltage.  Also
this sequence moves an RPM call from after the rail is on to
before it is powered up which saves a bit of power.

Change-Id: Ided5f9777879fa48fd594c84b31cec9cdf513098
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>

msm: kgsl: Add traces for the constraints API

This interface helps with debugging when an application
requests for a pwrlevel constraint to be set/unset. It
also traces when the constraints actually come into affect
and when they could be revoked.

Change-Id: I638cee89253a4c2383cf082193d735fd1e279ca0
Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>

Conflicts:
	drivers/gpu/msm/kgsl_pwrctrl.h

msm: kgsl: fix MIN power constraints in non-trivial cases

Switching from a MAX to a MIN power constraint in the same
context is broken.  So is switching from a MAX context constraint
to a MIN constraint on a different context.  Clarify constraint
ownership, update the timestamps accordingly, and reset constraints
when changed by the context.

Change-Id: Id27dbc20e2aac994101817af3857451c1703219e
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>

msm: kgsl: Remove the busy waiting loop from idle_check

Previously there were issues with extra long GPU sequences
running during the idle_check NAP attempt thwarting the
transition to NAP.  With the dispatcher architecture this
is much less likely to occur.  In addition the dispatcher
increases chances of a very short pause between a command
coming in and being submitted increasing the occurence of
"micro-NAPs" being caught by this loop.  These extremely
short NAP periods are actually a power loss on the CX rail.
Given that hw clock gating will take care of any long GPU
command tails remove the busy wait loop for power savings.

Change-Id: I4efc6215689c42ab03d4e478ad97839208d04004
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>

gpu: msm: Add missing trace include

Change-Id: Iefaa252a8cef43e5037f4bf3232560a44b11cb3f

msm: kgsl: Wait for dispatcher on adreno idle

When waiting for the adreno device to become idle wait for
the dispatcher to complete processing commands that are
already submitted to the ringbuffer and prevent dispatcher
from submitting more commands while a thread is waiting for
dispatcher to become idle. This is required to support mutiple
ringbuffers where it is not sufficient to just wait for current
ringbuffer to become idle. All ringbuffers need to be idle and
to do that dispatcher needs to run without submitting more
commands but retiring commands that have been submitted.

Change-Id: Idd36a8da3c230981476348682cd22aed6dab113c
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>

Conflicts:
	drivers/gpu/msm/adreno_dispatch.c

msm: kgsl: Add CFF capture for IBs

If CFF is enabled, when an IB is submitted to hardware
parse it to find all objects in it and dump them.

Change-Id: I2caecb6a9c912a59be4c0d2acdd3949c96196653
Signed-off-by: Shubhraprakash Das <sadas@codeaurora.org>

msm: kgsl: Use the correct method for exporting trace event functions

Use EXPORT_TRACEPOINT_SYMBOL instead of my lazy "trace" wrappers for
trace_kgsl_regwrite and trace_kgsl_issueibcmds thus saving lots of
code and a shred or two of dignity along the way.

Change-Id: Ic0dedbad4f54a7522edd2f9c3d017ba1e9dba505
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>

Conflicts:
	drivers/gpu/msm/adreno_ringbuffer.c
	drivers/gpu/msm/kgsl.h

msm: kgsl: Idle the dispatcher before writing perfcounter select

The GPU must be idle before writing to the perfcounter select
registers to avoid an AHB timeout. Idle the GPU before writing
to the register.

Change-Id: Ic0dedbadf8ad3f10f78ddf68520afe6cf98880e4
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>

Conflicts:
	drivers/gpu/msm/adreno.c

msm: kgsl: Avoid race conditions with GPU halt variable

1. Take the device mutex before we check for GPU halt.
It's quite possible that after checking gpu halt this
thread might be preempted by kernel, other thread can
update the gpu halt. This will lead to a situation
where other thread has requested to stop sending cmds
and this thread might be sending cmds to ringbuffer.

2. Handle multiple threads changing the halt variable.
It's possible that one thread has set the halt value
and other thread clears that value.

3. init_completion() cannot be used to reinitialize
completion when reusing completion object,
INIT_COMPLETION macro should be used instead.

CRs-Fixed: 667179
Change-Id: Ie41c69be35bfd3ca14f3ce782ab45efb70aaf46a
Signed-off-by: Prakash Kamliya <pkamliya@codeaurora.org>

Conflicts:
	drivers/gpu/msm/adreno_dispatch.c

msm: kgsl: Avoid another race condition with GPU halt

A race condition may occur while clearing GPU halt
from _adreno_start() in one thread and at the same
time decrementing it inside adreno_put_gpu_halt()
from adreno_dispatcher_idle_unsafe() in the other
thread. This can cause BUG_ON as "halt" value would
become negative.

Clearing GPU halt inside _adreno_start() should not
be required explicitly for below reasons:
1. "halt" is member of static global variable, so it
would be initialized to zero at the beginning.
2. Commands submission to GPU from the thread executing
_adreno_start() should be blocked until "halt" is reset
back to zero from adreno_dispatcher_idle_unsafe().

CRs-Fixed: 678633
Change-Id: I06bbf4ad751a72b2e943365c1ac1952f67ac299c
Signed-off-by: Prabhat Awasthi <pawasthi@codeaurora.org>
msm: kgsl: Keep the GPU from going into a slumber after a touch event

If the GPU is on the tail end of the nap period when a new touch event
occurs the system could go into slumber before the first render which
increases the startup latency. If a touch event occurs while in nap
just kick the idle timer back out to the interval timeout - this should
keep the system from transitioning to the lower power state only to
come right back up.

Change-Id: Ic0dedbad07cac877d0a71c69516b7c01841be1bd
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
sched: Remove get_online_cpus() usage

Remove get_online_cpus() usage from the scheduler; there's 4 sites that
use it:

 - sched_init_smp(); where its completely superfluous since we're in
   'early' boot and there simply cannot be any hotplugging.

 - sched_getaffinity(); we already take a raw spinlock to protect the
   task cpus_allowed mask, this disables preemption and therefore
   also stabilizes cpu_online_mask as that's modified using
   stop_machine. However switch to active mask for symmetry with
   sched_setaffinity()/set_cpus_allowed_ptr(). We guarantee active
   mask stability by inserting sync_rcu/sched() into _cpu_down.

 - sched_setaffinity(); we don't appear to need get_online_cpus()
   either, there's two sites where hotplug appears relevant:
    * cpuset_cpus_allowed(); for the !cpuset case we use possible_mask,
      for the cpuset case we hold task_lock, which is a spinlock and
      thus for mainline disables preemption (might cause pain on RT).
    * set_cpus_allowed_ptr(); Holds all scheduler locks and thus has
      preemption properly disabled; also it already deals with hotplug
      races explicitly where it releases them.

 - migrate_swap(); we can make stop_two_cpus() do the heavy lifting for
   us with a little trickery. By adding a sync_sched/rcu() after the
   CPU_DOWN_PREPARE notifier we can provide preempt/rcu guarantees for
   cpu_active_mask. Use these to validate that both our cpus are active
   when queueing the stop work before we queue the stop_machine works
   for take_cpu_down().

CRs-fixed: 647141
Change-Id: Id41e66659574f716de0e7c29f477e56a86db9404
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Cc: "Srivatsa S. Bhat" <srivatsa.bhat@linux.vnet.ibm.com>
Cc: Paul McKenney <paulmck@linux.vnet.ibm.com>
Cc: Mel Gorman <mgorman@suse.de>
Cc: Rik van Riel <riel@redhat.com>
Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com>
Cc: Andrea Arcangeli <aarcange@redhat.com>
Cc: Johannes Weiner <hannes@cmpxchg.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Link: http://lkml.kernel.org/r/20131011123820.GV3081@twins.programming.kicks-ass.net
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Git-commit: 6acce3ef84520537f8a09a12c9ddbe814a584dd2
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[kaushalk@codeaurora.org: get_online_cpus has only 3 sites of usage in
 kernel/sched/core.c of msm-3.10 so migrate_swap changes are not
 applicable here. stop_two_cpus related change is not applicable to
 msm-3.10, so skip it.]
Signed-off-by: Kaushal Kumar <kaushalk@codeaurora.org>

Conflicts:
	kernel/sched/core.c

sched: Remove extra put_online_cpus() inside sched_setaffinity()

Commit 6acce3ef8:

	sched: Remove get_online_cpus() usage

has left one extra put_online_cpus() inside sched_setaffinity(),
remove it to fix the WARN:

   ------------[ cut here ]------------
   WARNING: CPU: 0 PID: 3166 at kernel/cpu.c:84 put_online_cpus+0x43/0x70()
   ...
   [<ffffffff810c3fef>] put_online_cpus+0x43/0x70 [
   [<ffffffff810efd59>] sched_setaffinity+0x7d/0x1f9 [
   ...

CRs-fixed: 647141
Change-Id: I33f799f30a963db3e9459832832e9c786931c8c2
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Tested-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Michael Wang <wangyun@linux.vnet.ibm.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/526DD0EE.1090309@linux.vnet.ibm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Git-commit: ac9ff7997b6f2b31949dcd2495ac671fd9ddc990
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Kaushal Kumar <kaushalk@codeaurora.org>

sched: Fix endless sync_sched/rcu() loop inside _cpu_down()

Commit 6acce3ef8:

	sched: Remove get_online_cpus() usage

tries to do sync_sched/rcu() inside _cpu_down() but triggers:

	INFO: task swapper/0:1 blocked for more than 120 seconds.
	...
	[<ffffffff811263dc>] synchronize_rcu+0x2c/0x30
	[<ffffffff81d1bd82>] _cpu_down+0x2b2/0x340
	...

It was caused by that in the rcu boost case we rely on smpboot thread to
finish the rcu callback, which has already been parked before sync in here
and leads to the endless sync_sched/rcu().

This patch exchanges the sequence of smpboot_park_threads() and
sync_sched/rcu() to fix the bug.

CRs-fixed: 647141
Change-Id: Ia8b325d7c3c778f428d9fb51271977c849df32ad
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Tested-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Michael Wang <wangyun@linux.vnet.ibm.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/5282EDC0.6060003@linux.vnet.ibm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Git-commit: 106dd5afde3cd10db7e1370b6ddc77f0b2496a75
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Kaushal Kumar <kaushalk@codeaurora.org>

sched: Remove synchronize rcu/sched calls from _cpu_down

There is no need for sync_sched() in _cpu_down as stop_machine()
provides that barrier implicitly. Removing it also helps improve
hot-unplug latency.
The sync_sched/rcu were earlier removed for the same reason by the
commit 9ee349ad6d326df3633d43f54202427295999c47, but recently got
added as part of commit c4575f83b9fe87bb57b737bc8a667f746a20320a.

CRs-Fixed: 667325
Change-Id: I97763004454d082d3cc2d9d9dbef7da923608600
Signed-off-by: Kaushal Kumar <kaushalk@codeaurora.org>
ion: Use dma_free_attrs for freeing secure memory

Secure CMA memory is allocated using DMA_ATTR_NO_KERNEL_MAPPING.
Free the memory with the same attribute.

Change-Id: I67289af68763c5b6d4b0f3d828174ad28b711642
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>

staging: ion: remove struct ion_page_pool_item

The page pool uses an internal data structure, ion_page_pool_item, for
wrapping pooled pages and constructing a list. As the struct page
already provides ways for doing exactly the same thing, we do not need
to reinvent the wheel. This commit removes the data structure and slab
allocations for it.

Change-Id: I3653a71337abc26c0cd6791be7cb175055281036
Signed-off-by: Heesub Shin <heesub.shin@samsung.com>
Reviewed-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Tested-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Git-commit: 38c003b113ceab37f80d020999d3ec2cbf784da3
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>

staging: ion: shrink highmem pages on kswapd

ION system heap keeps pages in its pool for better performance. When the
system is under memory pressure, slab shrinker calls the callback
registered and then the pages pooled get freed.

When the shrinker is called, it checks gfp_mask and determines whether
the pages from highmem need to be freed or the pages from lowmem.
Usually, slab shrinker is invoked on kswapd context which gfp_mask is
always GFP_KERNEL, so only lowmem pages are released on kswapd context.
This means that highmem pages in the pool are never reclaimed until
direct reclaim occurs. This can be problematic when the page pool holds
excessive amounts of highmem.

For now, the shrinker callback cannot know exactly which zone should be
targeted for reclamation, as enough information are not passed to. Thus,
it makes sense to shrink both lowmem and highmem zone on kswapd context.

Change-Id: Ibf21e36e6d370967fa9166d6e5d66aec98851478
Reported-by: Wonseo Choi <wonseo.choi@samsung.com>
Signed-off-by: Heesub Shin <heesub.shin@samsung.com>
Reviewed-by: Mitchel Humpherys <mitchelh@codeaurora.org>
Tested-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Git-commit: 0cd2dc4db3ba23ff8ab38b8ae81b126626f795d5
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git
[shashim@codeaurora.org: resolve trivial merge conflict]
Signed-off-by: Shiraz Hashim <shashim@codeaurora.org>
smp: Fix SMP function call empty cpu mask race

I get the following warning every day with v3.7, once or
twice a day:

  [ 2235.186027] WARNING: at /mnt/sda7/kernel/linux/arch/x86/kernel/apic/ipi.c:109 default_send_IPI_mask_logical+0x2f/0xb8()

As explained by Linus as well:

 |
 | Once we've done the "list_add_rcu()" to add it to the
 | queue, we can have (another) IPI to the target CPU that can
 | now see it and clear the mask.
 |
 | So by the time we get to actually send the IPI, the mask might
 | have been cleared by another IPI.
 |

This patch also fixes a system hang problem, if the data->cpumask
gets cleared after passing this point:

        if (WARN_ONCE(!mask, "empty IPI mask"))
                return;

then the problem in commit 83d349f35e1a ("x86: don't send an IPI to
the empty set of CPU's") will happen again.

Signed-off-by: Wang YanQing <udknight@gmail.com>
Acked-by: Linus Torvalds <torvalds@linux-foundation.org>
Acked-by: Jan Beulich <jbeulich@suse.com>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: peterz@infradead.org
Cc: mina86@mina86.org
Cc: srivatsa.bhat@linux.vnet.ibm.com
Cc: <stable@kernel.org>
Link: http://lkml.kernel.org/r/20130126075357.GA3205@udknight
[ Tidied up the changelog and the comment in the code. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>

smp: make smp_call_function_many() use logic similar to smp_call_function_single()

I'm testing swapout workload in a two-socket Xeon machine.  The workload
has 10 threads, each thread sequentially accesses separate memory
region.  TLB flush overhead is very big in the workload.  For each page,
page reclaim need move it from active lru list and then unmap it.  Both
need a TLB flush.  And this is a multthread workload, TLB flush happens
in 10 CPUs.  In X86, TLB flush uses generic smp_call)function.  So this
workload stress smp_call_function_many heavily.

Without patch, perf shows:
+  24.49%  [k] generic_smp_call_function_interrupt
-  21.72%  [k] _raw_spin_lock
   - _raw_spin_lock
      + 79.80% __page_check_address
      + 6.42% generic_smp_call_function_interrupt
      + 3.31% get_swap_page
      + 2.37% free_pcppages_bulk
      + 1.75% handle_pte_fault
      + 1.54% put_super
      + 1.41% grab_super_passive
      + 1.36% __swap_duplicate
      + 0.68% blk_flush_plug_list
      + 0.62% swap_info_get
+   6.55%  [k] flush_tlb_func
+   6.46%  [k] smp_call_function_many
+   5.09%  [k] call_function_interrupt
+   4.75%  [k] default_send_IPI_mask_sequence_phys
+   2.18%  [k] find_next_bit

swapout throughput is around 1300M/s.

With the patch, perf shows:
-  27.23%  [k] _raw_spin_lock
   - _raw_spin_lock
      + 80.53% __page_check_address
      + 8.39% generic_smp_call_function_single_interrupt
      + 2.44% get_swap_page
      + 1.76% free_pcppages_bulk
      + 1.40% handle_pte_fault
      + 1.15% __swap_duplicate
      + 1.05% put_super
      + 0.98% grab_super_passive
      + 0.86% blk_flush_plug_list
      + 0.57% swap_info_get
+   8.25%  [k] default_send_IPI_mask_sequence_phys
+   7.55%  [k] call_function_interrupt
+   7.47%  [k] smp_call_function_many
+   7.25%  [k] flush_tlb_func
+   3.81%  [k] _raw_spin_lock_irqsave
+   3.78%  [k] generic_smp_call_function_single_interrupt

swapout throughput is around 1400M/s.  So there is around a 7%
improvement, and total cpu utilization doesn't change.

Without the patch, cfd_data is shared by all CPUs.
generic_smp_call_function_interrupt does read/write cfd_data several times
which will create a lot of cache ping-pong.  With the patch, the data
becomes per-cpu.  The ping-pong is avoided.  And from the perf data, this
doesn't make call_single_queue lock contend.

Next step is to remove generic_smp_call_function_interrupt() from arch
code.

Signed-off-by: Shaohua Li <shli@fusionio.com>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Jens Axboe <axboe@kernel.dk>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Conflicts:
	include/linux/smp.h

Change-Id: I71e497695fa343b3edc6ec77a6dc1698f0e07a86
msm: clock-krait-8974: Add support to read SVS PVS bin

On some targets, the PVS table is split into SVS freq table and
the turbo freq table. Add the support to read the SVS PVS bin and
construct the complete PVS table.

Change-Id: I5a30d295efa8d0cf0a74747f29c39ca5c3faa3d4
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
lm3630: Clean up the lm3630 driver

Change-Id: I380ef4bb8bd66966a7e31a7d2de85a134d2b5a2b
input: touchscreen: synaptics_dsx: Generate the hardware ts on interrupt

We were generating the hardware timestamps when processing the workqueue,
which can happen "much" later than the actual irq. Increase the ts
reporting precision by generating the timestamp on the interrupt handler,
and get rid of the work queue entirely.

Change-Id: I171aad3d4a8f40eb7f8ab40abea0e9f1df2f1879
ARM: bitops: prefetch the destination word for write prior to strex

The cost of changing a cacheline from shared to exclusive state can be
significant, especially when this is triggered by an exclusive store,
since it may result in having to retry the transaction.

This patch prefixes our atomic bitops implementation with prefetchw,
to try and grab the line in exclusive state from the start. The testop
macro is left alone, since the barrier semantics limit the usefulness
of prefetching data.

Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>

ARM: 7907/1: lib: delay-loop: Add align directive to fix BogoMIPS calculation

Currently mx53 (CortexA8) running at 1GHz reports:
Calibrating delay loop... 663.55 BogoMIPS (lpj=3317760)

Tom Evans verified that alignments of 0x0 and 0x8 run the two instructions of __loop_delay in one clock cycle (1 clock/loop), while alignments of 0x4 and 0xc take 3 clocks to run the loop twice. (1.5 clock/loop)

The original object code looks like this:

00000010 <__loop_const_udelay>:
  10:	e3e01000 	mvn	r1, #0
  14:	e51f201c 	ldr	r2, [pc, #-28]	; 0 <__loop_udelay-0x8>
  18:	e5922000 	ldr	r2, [r2]
  1c:	e0800921 	add	r0, r0, r1, lsr #18
  20:	e1a00720 	lsr	r0, r0, #14
  24:	e0822b21 	add	r2, r2, r1, lsr #22
  28:	e1a02522 	lsr	r2, r2, #10
  2c:	e0000092 	mul	r0, r2, r0
  30:	e0800d21 	add	r0, r0, r1, lsr #26
  34:	e1b00320 	lsrs	r0, r0, #6
  38:	01a0f00e 	moveq	pc, lr

0000003c <__loop_delay>:
  3c:	e2500001 	subs	r0, r0, #1
  40:	8afffffe 	bhi	3c <__loop_delay>
  44:	e1a0f00e 	mov	pc, lr

After adding the 'align 3' directive to __loop_delay (align to 8 bytes):

00000010 <__loop_const_udelay>:
  10:	e3e01000 	mvn	r1, #0
  14:	e51f201c 	ldr	r2, [pc, #-28]	; 0 <__loop_udelay-0x8>
  18:	e5922000 	ldr	r2, [r2]
  1c:	e0800921 	add	r0, r0, r1, lsr #18
  20:	e1a00720 	lsr	r0, r0, #14
  24:	e0822b21 	add	r2, r2, r1, lsr #22
  28:	e1a02522 	lsr	r2, r2, #10
  2c:	e0000092 	mul	r0, r2, r0
  30:	e0800d21 	add	r0, r0, r1, lsr #26
  34:	e1b00320 	lsrs	r0, r0, #6
  38:	01a0f00e 	moveq	pc, lr
  3c:	e320f000 	nop	{0}

00000040 <__loop_delay>:
  40:	e2500001 	subs	r0, r0, #1
  44:	8afffffe 	bhi	40 <__loop_delay>
  48:	e1a0f00e 	mov	pc, lr
  4c:	e320f000 	nop	{0}

, which now reports:
Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)

Some more test results:

On mx31 (ARM1136) running at 532 MHz, before the patch:
Calibrating delay loop... 351.43 BogoMIPS (lpj=1757184)

On mx31 (ARM1136) running at 532 MHz after the patch:
Calibrating delay loop... 528.79 BogoMIPS (lpj=2643968)

Also tested on mx6 (CortexA9) and on mx27 (ARM926), which shows the same
BogoMIPS value before and after this patch.

Reported-by: Tom Evans <tom_usenet@optusnet.com.au>
Suggested-by: Tom Evans <tom_usenet@optusnet.com.au>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7404/1: cmpxchg64: use atomic64 and local64 routines for cmpxchg64

The cmpxchg64 routines for ARMv6+ CPUs replicate inline assembly that
already exists for atomic64 operations. Furthermore, the cmpxchg64 code
uses the "memory" constraint in the clobber list rather than identifying
the region of memory that is actually modified.

This patch replaces the ARMv6+ cmpxchg64 code with macros that expand to
the atomic64_ and local64_ variants, casting the pointer parameter to
the appropriate container type.

Cc: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7720/1: ARM v6/v7 cmpxchg64 shouldn't clear upper 32 bits of the old/new value

The implementation of cmpxchg64() for the ARM v6 and v7 architecture
casts parameter 2 and 3 (the old and new 64bit values) to an unsigned
long before calling the atomic_cmpxchg64() function. This clears
the top 32 bits of the old and new values, resulting in the wrong
values being compare-exchanged. Luckily, this only appears to be used
for 64-bit sched_clock, which we don't (yet) have on ARM.

This bug was introduced by commit 3e0f5a15f500 ("ARM: 7404/1: cmpxchg64:
use atomic64 and local64 routines for cmpxchg64").

Cc: <stable@vger.kernel.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Jaccon Bastiaansen <jaccon.bastiaansen@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7852/1: cmpxchg: implement barrier-less cmpxchg64_local

Our cmpxchg64 macros are wrappers around atomic64_cmpxchg. Whilst this is
great for code re-use, there is a case for barrier-less cmpxchg where it
is known to be safe (for example cmpxchg64_local and cmpxchg-based
lockrefs).

This patch introduces a 64-bit cmpxchg implementation specifically
for the cmpxchg64_* macros, so that it can be later used by the lockref
code.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7853/1: cmpxchg: implement cmpxchg64_relaxed

This patch introduces cmpxchg64_relaxed for arm, which performs a 64-bit
cmpxchg operation without barrier semantics. cmpxchg64_local is updated
to use the new operation.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

ARM: 7984/1: prefetch: add prefetchw invocations for barriered atomics

After a bunch of benchmarking on the interaction between dmb and pldw,
it turns out that issuing the pldw *after* the dmb instruction can
give modest performance gains (~3% atomic_add_return improvement on a
dual A15).

This patch adds prefetchw invocations to our barriered atomic operations
including cmpxchg, test_and_xxx and futexes.

Change-Id: Id6ebfe82ff9578c27e2b745e2cce167200112606
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>