defconfig: msm: Enable KSM for msm8610

Kernel Samepage Merging (KSM) saves memory by merging
pages with the same content.

Change-Id: I89468761e03b08c4700d2aa0f7c8ccad45dd0550
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
android/lowmemorykiller: Account for total_swapcache_pages

The lowmemorykiller relies on NR_FILE_PAGES when measureing
the amount of reclaimable memory in the system.
However when swap is enabled swap cache pages are counted
in NR_FILE_PAGES, and swap cache pages aren't as reclaimable
in low memory as file cache pages. Therefore a large swap
cache can result in the lowmemorykiller not running and
an OOM occuring.

In order to ensure the lowmemorykiller properly evaluates the
amount of reclaimable memory don't count the swap cache pages.

Change-Id: I38239283e572f814b277c718eaf6be7f92abacbb
Signed-off-by: Liam Mark <lmark@codeaurora.org>
staging: zsmalloc: Ensure handle is never 0 on success

zsmalloc encodes a handle using the pfn and an object
index. On hardware platforms with physical memory starting
at 0x0 the pfn can be 0. This causes the encoded handle to be
0 and is incorrectly interpreted as an allocation failure.

This issue affects all current and future SoCs with physical
memory starting at 0x0. All MSM8974 SoCs which includes
Google Nexus 5 devices are affected.

To prevent this false error we ensure that the encoded handle
will not be 0 when allocation succeeds.

Change-Id: I5ad31712be4dd5105ebee81fa95927039c0f6935
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
tick: Dynamically set broadcast irq affinity

When a cpu goes to a deep idle state where its local timer is
shutdown, it notifies the time frame work to use the broadcast timer
instead.  Unfortunately, the broadcast device could wake up any CPU,
including an idle one which is not concerned by the wake up at all. So
in the worst case an idle CPU will wake up to send an IPI to the CPU
whose timer expired.

Provide an opt-in feature CLOCK_EVT_FEAT_DYNIRQ which tells the core
that is should set the interrupt affinity of the broadcast interrupt
to the cpu which has the earliest expiry time. This avoids unnecessary
spurious wakeups and IPIs.

[ tglx: Adopted to cpumask rework, silenced an uninitialized warning,
  massaged changelog ]

Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: viresh.kumar@linaro.org
Cc: jacob.jun.pan@linux.intel.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: santosh.shilimkar@ti.com
Cc: linaro-kernel@lists.linaro.org
Cc: patches@linaro.org
Cc: rickard.andersson@stericsson.com
Cc: vincent.guittot@linaro.org
Cc: linus.walleij@stericsson.com
Cc: john.stultz@linaro.org
Link: http://lkml.kernel.org/r/1362219013-18173-3-git-send-email-daniel.lezcano@linaro.org
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

Change-Id: I6a880a39dd595526b80a6d72b88be74163513da9
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
cpuidle: make a single register function for all

The usual scheme to initialize a cpuidle driver on a SMP is:

	cpuidle_register_driver(drv);
	for_each_possible_cpu(cpu) {
		device = &per_cpu(cpuidle_dev, cpu);
		cpuidle_register_device(device);
	}

This code is duplicated in each cpuidle driver.

On UP systems, it is done this way:

	cpuidle_register_driver(drv);
	device = &per_cpu(cpuidle_dev, cpu);
	cpuidle_register_device(device);

On UP, the macro 'for_each_cpu' does one iteration:

        for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask)

Hence, the initialization loop is the same for UP than SMP.

Beside, we saw different bugs / mis-initialization / return code unchecked in
the different drivers, the code is duplicated including bugs. After fixing all
these ones, it appears the initialization pattern is the same for everyone.

Please note, some drivers are doing dev->state_count = drv->state_count. This is
not necessary because it is done by the cpuidle_enable_device function in the
cpuidle framework. This is true, until you have the same states for all your
devices. Otherwise, the 'low level' API should be used instead with the specific
initialization for the driver.

Let's add a wrapper function doing this initialization with a cpumask parameter
for the coupled idle states and use it for all the drivers.

That will save a lot of LOC, consolidate the code, and the modifications in the
future could be done in a single place. Another benefit is the consolidation of
the cpuidle_device variable which is now in the cpuidle framework and no longer
spread accross the different arch specific drivers.

Change-Id: I8f75188d5770871620f758c2973b74384ac570d5
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
ARM: mm: implement LoUIS API for cache maintenance ops

ARM v7 architecture introduced the concept of cache levels and related
control registers. New processors like A7 and A15 embed an L2 unified cache
controller that becomes part of the cache level hierarchy. Some operations in
the kernel like cpu_suspend and __cpu_disable do not require a flush of the
entire cache hierarchy to DRAM but just the cache levels belonging to the
Level of Unification Inner Shareable (LoUIS), which in most of ARM v7 systems
correspond to L1.

The current cache flushing API used in cpu_suspend and __cpu_disable,
flush_cache_all(), ends up flushing the whole cache hierarchy since for
v7 it cleans and invalidates all cache levels up to Level of Coherency
(LoC) which cripples system performance when used in hot paths like hotplug
and cpuidle.

Therefore a new kernel cache maintenance API must be added to cope with
latest ARM system requirements.

This patch adds flush_cache_louis() to the ARM kernel cache maintenance API.

This function cleans and invalidates all data cache levels up to the
Level of Unification Inner Shareable (LoUIS) and invalidates the instruction
cache for processors that support it (> v7).

This patch also creates an alias of the cache LoUIS function to flush_kern_all
for all processor versions prior to v7, so that the current cache flushing
behaviour is unchanged for those processors.

v7 cache maintenance code implements a cache LoUIS function that cleans and
invalidates the D-cache up to LoUIS and invalidates the I-cache, according
to the new API.

Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>

Change-Id: I561c3b187b5b87b25de07ea82a4ef73a42761e27
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: pm: idle-v7 clean up

Legacy platforms are not expected to use the mainline
anymore. Unsupported targets are MSM7X01A, MSM7X25,
MSM7X27, MSM7X30, QSD8X50, MSM8X60, MSM8960,MSM8930,
APQ8064, FSM9XXX, MSM9615, MSM8625, MSM9625, MSM7X27A.

Remove unused code in idle-v7 and its related files.

Change-Id: If1fbf9eead91d3410c5c5e75cb92824b110b1138
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: pm: cleanup spm code related to SAW2_V1

Code related to SAW2_V1 is removed. The relevant targets
are no more built on mainline.

Change-Id: Ie3f5a9f1dab0026b02e55384b6c620db774982b1
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: idle: Use ARM suspend/resume APIs to restore during warmboot

ARM generic cpu_suspend/resume APIs restore the necessary CP15 registers
to a known state when resuming from a reset state. Use of generic
suspend/resume APIs allows the msm warmboot code to not care about
restoring core registers used by ARM kernel. Also, the PM subsystem no
longer needs to allocate page table or uncached memory to save CPU
registers.

While at it convert most of the assembler code into respective C
function except for warmboot code that executes with MMU turned off.
Also, the idle subsystem no longer needs to manage a  page table or
uncached memory to save CPU registers.

Change-Id: I78a75d0a3c703390eec476199c7ca2786360e12a
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
ARM: Set CLK_EVT_FEAT_DYNIRQ flag memory mapped timers

Memory mapped timers are used as broadcast timers to wake up a core
across reset. CLK_EVT_FEAT_DYNIRQ ensures only the intended cores are
woken up instead of the default core that they are routed to, thereby
saving power.

Change-Id: I535faa0d1fd328fefe4422a6f362b17c94ab5b8e
Signed-off-by: Karthik Parsha <kparsha@codeaurora.org>
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Revert "msm: lpm_levels: Adjust latency for Multi core cases"

This reverts commit b4e82b5c6ffac10efaae98213a57988ad424f2e7. The
performance and power benefits obtained with these changes were minimal
and hence removing this change.

Change-Id: I8495d4e7a669a5a0eb519e853eb0d45508a64c1a
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: pm: Rename pm-8x60.c to msm-pm.c

pm-8x60.c doesn't accurately reflect the current list of targets that
are supported. So renaming them to msm-pm.c to be more inline with the
msm chipsets.

Change-Id: Iefa8150885f8da136de7cba4a122ec901a171a02
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: pm: Rearchitect power management code

The existing PM code relies on a levels table to determine the various
sleep modes including the system sleep states. Splitting them into cpu
and system/cluster specific levels is a more appropriate representation
of the existing system. As a part of this rearchitecture, the decision
to enter a low power mode is made within lpm_levels module. Unlike
earlier, the decision was split between pm-8x60 and lpm_levels.

To this effect, the lpm_levels directly registers with the cpuidle
driver instead of relying on a glue msm-cpuidle driver. The
functionality of the cpuidle driver was limited to calling into a PM
driver and without providing any additional functionality.

While at it, also remove any references to unused enums and
functionality.

Change-Id: I474cc85c6220473fdaa87e14e3b0a199e95d7eb7
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: clock-krait-8974: Change ref count behavior at boot

Set up the refcount of the L2 clock to be equal to the number of online
cores. This allows the clients of the CPU/L2 clocks that enable/disable
them to be agnostic of the no. of cores that are online.

For example, the CPU idle code can call clk_disable() on the L2 clock from
all the cores' idle path without having to figure out if it's the last
active core. If the core is the last core that's active, the ref count will
go from 1 to 0 and the clock would get disabled.

Also update cpufreq driver behavior to accomodate this change.

Change-Id: If253a85ad62f0a6a78452dafc7afe86bd112cf73
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: lpm_levels: Support for RPM PC on all cores

When more than one core is online, the current model prevent entering
idle power collapse on all cores and the deepest sleep mode that a
cpu could enter is standalone power collapse. To achieve better power
savings when several cores are online all the time, it is important for
multiple cores to enter a deeper system sleep state by configuring L2
and RPM.

Each core entering the deepest sleep mode increments a counter. The
last core to enter the deepest sleep mode will acquire a lock and will
be responsible for configuring the system low power mode.  cpus. The
last core going down will configure the system wide resources with the
lock held. If a core were to wakeup during this time, it would have to
wait for the lock to be released before it can continue to resume. The
last core releases the lock after configuring the system resources at
which point, the core that resumed from power collapse would reset the
system resources before continuing to run to ensure that the shared
resources are programmed for a safe state.

With this change the idle PC becomes more of a soft state where each
core identifies that its safe to enter a system sleep state. The
decision to enter a system sleep mode is based on the next wakeup event
across all cores. With not all cores encoutering latency associated with
system sleep modes, the residency of idle PC mode will be lower than
what it has been previously acheived. However, the residency of the
system sleep states should be unaffected.

Each core as its power collapsed disables the HFPLL and switches to
GFPLL in the event of a power collapse. During this time, each cores
removes its vote to keep L2 enabled. To ensure that there are enough
votes for keep L2 on, set the number of L2 votes to number of online
cpus in cpufreq.c

Change-Id: If6a8e181bdb9c7bae8066fb804de13caa48bad3b
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
msm: pm: Set affinity of PM irqs to next scheduled CPU

Modify the affinity of the interrupts associated with PM driver to the cpu
that will wakeup for the next expiring timer.

Change-Id: I6a1b25538a6d12bada3345a17b3ed4ff181ac089
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
Merge "staging: zsmalloc: Ensure handle is never 0 on success" into kk_3.5_rb1.14
Merge "defconfig: msm: Enable KSM for msm8610" into kk_3.5_rb1.14
Merge changes I78a75d0a,Ie3f5a9f1,If1fbf9ee,I8f75188d into kk_3.5_rb1.14

* changes:
  msm: idle: Use ARM suspend/resume APIs to restore during warmboot
  msm: pm: cleanup spm code related to SAW2_V1
  msm: pm: idle-v7 clean up
  cpuidle: make a single register function for all
Merge changes I6a1b2553,If6a8e181,If253a85a,I474cc85c,Iefa81508,I8495d4e7,I535faa0d into kk_3.5_rb1.14

* changes:
  msm: pm: Set affinity of PM irqs to next scheduled CPU
  msm: lpm_levels: Support for RPM PC on all cores
  msm: clock-krait-8974: Change ref count behavior at boot
  msm: pm: Rearchitect power management code
  msm: pm: Rename pm-8x60.c to msm-pm.c
  Revert "msm: lpm_levels: Adjust latency for Multi core cases"
  ARM: Set CLK_EVT_FEAT_DYNIRQ flag memory mapped timers