* Added support for portWrite and portMode
* Don't force the port as output in the portWrite function.
  This is done by IoTPy, or with the function portMode.
* Added a function to read port.
  I still have a problem with PIN10 and 11...
* Bug fix
* Refactored the PORT mapping. I still have a problem when port = 1 and i = 3, but I don't know why ...
* Fixed the bug with the pin 11.
* Added support for DHT11 and DHT22
* Added a synchro and cleanup. This help to decrease the CRC error rate.
* To detect a 1 or 0, it's not really necessary to detect the time.
  A bit is always composed of a LOW state of 50us, and a HIGH state
  of 26us for 0 and 70us for 1.
  So, if the HIGH state is longuer than the LOW state, it's a 1,
  otherwise it's a 0.
  This code works fine and the CRC error rate is now almost equal
  to zero. I now have to add some timeout and protections.
* Added protections.
  If the start burst is not detected, return SFP_ERR.
* Better protections
* Fixed issue #17 of nodesign/weio.
  To avoid glitches on PWM when the value is updated, the moment when
  the new compare value is stored into CRx must be sync with CT.
* lpc_config_gpioInit() should be called before CDC_Init() to be able to use the UART bridge.
  lpc_config_gpioInit() set all GPIO to a default state, and override the UART configuration on
  PIO0_18 and PIO0_19.
  It was working on debug, but not on release.